diff options
| author | Tom Rini <trini@konsulko.com> | 2022-10-20 08:58:25 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-10-20 08:58:25 -0400 |
| commit | dc3cb0abf41191aad62a6537ce8734a4f5339888 (patch) | |
| tree | 16bb7bb9f529012b9b86666ec6af722ab9c6bdf9 /drivers/clk | |
| parent | 73ceadcd7280cb552119e24ca092d626b12626a6 (diff) | |
| parent | 19fb40a5e7ee815a703ffdcc7c0fdb7933762256 (diff) | |
Merge tag 'clk-2023.01' of https://source.denx.de/u-boot/custodians/u-boot-clk
Clock patches for 2023.01
This contains various fixes (some long overdue) for the next release.
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk-uclass.c | 20 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk_pll.c | 6 |
2 files changed, 21 insertions, 5 deletions
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index b89c77bf79..2f9635524c 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -505,7 +505,7 @@ struct clk *clk_get_parent(struct clk *clk) return pclk; } -long long clk_get_parent_rate(struct clk *clk) +ulong clk_get_parent_rate(struct clk *clk) { const struct clk_ops *ops; struct clk *pclk; @@ -544,6 +544,19 @@ ulong clk_round_rate(struct clk *clk, ulong rate) return ops->round_rate(clk, rate); } +static void clk_get_priv(struct clk *clk, struct clk **clkp) +{ + *clkp = clk; + + /* get private clock struct associated to the provided clock */ + if (CONFIG_IS_ENABLED(CLK_CCF)) { + /* Take id 0 as a non-valid clk, such as dummy */ + if (clk->id) + clk_get_by_id(clk->id, clkp); + } +} + +/* clean cache, called with private clock struct */ static void clk_clean_rate_cache(struct clk *clk) { struct udevice *child_dev; @@ -563,6 +576,7 @@ static void clk_clean_rate_cache(struct clk *clk) ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; + struct clk *clkp; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); if (!clk_valid(clk)) @@ -572,8 +586,10 @@ ulong clk_set_rate(struct clk *clk, ulong rate) if (!ops->set_rate) return -ENOSYS; + /* get private clock struct used for cache */ + clk_get_priv(clk, &clkp); /* Clean up cached rates for us and all child clocks */ - clk_clean_rate_cache(clk); + clk_clean_rate_cache(clkp); return ops->set_rate(clk, rate); } diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 8d2aaf5b84..09b97cf57a 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -31,7 +31,7 @@ static struct rockchip_pll_rate_table rockchip_auto_table; #define RK3036_PLLCON1_DSMPD_SHIFT 12 #define RK3036_PLLCON2_FRAC_MASK 0xffffff #define RK3036_PLLCON2_FRAC_SHIFT 0 -#define RK3036_PLLCON1_PWRDOWN_SHIT 13 +#define RK3036_PLLCON1_PWRDOWN_SHIFT 13 #define MHZ 1000000 #define KHZ 1000 @@ -207,7 +207,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power down */ rk_setreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); rk_clrsetreg(base + pll->con_offset, (RK3036_PLLCON0_POSTDIV1_MASK | @@ -231,7 +231,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power Up */ rk_clrreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); /* waiting for pll lock */ while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) |