Merge tag 'xilinx-for-v2023.01-rc1-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2023.01-rc1 (round 2)

xilinx:
- Add support for new Versal NET SOC

zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio

versal:
- Config cleanup

2 files changed, 2 insertions, 1 deletions

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index fd9e1a80c6a..09aa97ee8c0 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -184,7 +184,7 @@ config CLK_VERSACLOCK
 
 config CLK_VERSAL
 	bool "Enable clock driver support for Versal"
-	depends on ARCH_VERSAL
+	depends on (ARCH_VERSAL || ARCH_VERSAL_NET)
 	select ZYNQMP_FIRMWARE
 	help
 	  This clock driver adds support for clock realted settings for
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index a9dd57b098f..b2f62061cea 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -739,6 +739,7 @@ static struct clk_ops versal_clk_ops = {
 
 static const struct udevice_id versal_clk_ids[] = {
 	{ .compatible = "xlnx,versal-clk" },
+	{ .compatible = "xlnx,versal-net-clk" },
 	{ }
 };