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authorMarek BehĂșn <marek.behun@nic.cz>2020-04-15 00:59:18 +0200
committerStefan Roese <sr@denx.de>2020-04-22 14:28:15 +0200
commit239f424f497dcda32322d3ee990f20d26a5a2f47 (patch)
tree03d98bd80c8bde4f47f41a6d78a85494c081f5e0 /drivers/clk
parentbdcb29960e3a9558803632783b922f26993d219e (diff)
clk: armada-37xx-periph: fix DDR PHY clock divider values
Register value table for DDR PHY clock divider are wrong. They should be 0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current values do not make sense, since 2 cannot be achieved, because the register is only 1 bit long (mask is set to 1). This fixes clk dump reporting DDR PHY clock rate differently from Linux. Signed-off-by: Marek BehĂșn <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/mvebu/armada-37xx-periph.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 068e48ea04..855f979b4f 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -89,8 +89,8 @@ static const struct clk_div_table div_table1[] = {
};
static const struct clk_div_table div_table2[] = {
- { 2, 1 },
- { 4, 2 },
+ { 2, 0 },
+ { 4, 1 },
{ 0, 0 },
};