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| author | Tom Rini <trini@konsulko.com> | 2020-05-14 08:44:06 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-14 08:44:06 -0400 |
| commit | e2b86e23cebc9dfaca2e7b7e53b10fa27d09f4e9 (patch) | |
| tree | 0e8b20ee7e4b9426913dc905392386c1c28ee0f2 /drivers/clk | |
| parent | fe16786149c8f1b2db95ed614a760bc443da6472 (diff) | |
| parent | 1b28a5e2b00a9bf3523cc63694baa03f23604619 (diff) | |
Merge tag 'u-boot-stm32-20200514' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- stm32mp1: migrate MTD and DFU configuration in Kconfig
- stm32mp1: add command stm32prog
- stm32mp1: several board and arch updates
- stm32mp1: activate data cache in SPL and before relocation
- Many improvment for AV96 board and DHCOR SoM
(add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM
Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM)
- clk: stm32mp1: fix CK_MPU calculation
- DT alignment of stm32mp1 device tree with Linux 5.7-rc2
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk_stm32mp1.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 50df8425bf7..0d0ea43fd20 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -954,10 +954,11 @@ static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p) case RCC_MPCKSELR_PLL: case RCC_MPCKSELR_PLL_MPUDIV: clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P); - if (p == RCC_MPCKSELR_PLL_MPUDIV) { + if ((reg & RCC_SELR_SRC_MASK) == + RCC_MPCKSELR_PLL_MPUDIV) { reg = readl(priv->base + RCC_MPCKDIVR); - clock /= stm32mp1_mpu_div[reg & - RCC_MPUDIV_MASK]; + clock >>= stm32mp1_mpu_div[reg & + RCC_MPUDIV_MASK]; } break; } |