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authorTom Rini <trini@konsulko.com>2023-01-27 10:15:39 -0500
committerTom Rini <trini@konsulko.com>2023-01-27 10:15:39 -0500
commit9ddbd70ff9f70b69053282e631c8886830e0fa5d (patch)
tree5cde271c461d66fe788dc6eacd8d95127dc8fdb7 /drivers/clk
parentb3b6cc28c240507503e471edc105e2d93a277126 (diff)
parentf0f86d39fec73479d4904e6d5b9db01a29597d58 (diff)
Merge tag 'xilinx-for-v2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx chnages for v2023.04-rc1 makefile: - Add multi_dtb_fit dependency clk: - Handle error cases microblaze: - Disable falcon mode and cleanup code around xilinx: - Enable regular expression matching in board_fit_config_name_match() - Fix FRU handling for 0xC1 format - Fix Xilinx legacy format eeprom parsing zynqmp: - Some DT updates/cleanups - Fix IDcode for xck24 - Remove empty mini config files - Add support for k24 versal: - Remove empty mini config files versal_net: - Setup timer when runs in EL3 - Build u-boot.elf for mini configurations zynq-gem: - Add support for new compatible strings - Remove support for Avnet Ultrazedev SOM - Handle SGMII with PCS phy spi: - Add support for gigadevice parts misc: - Remove CONFIG_TARGET_VENUS ifdef - Add missing headers to remove sparse warnings
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/clk_versal.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index 76fde00491..faebbab1c6 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -657,7 +657,9 @@ static int versal_clk_probe(struct udevice *dev)
if (ret < 0)
return -EINVAL;
- versal_clock_setup();
+ ret = versal_clock_setup();
+ if (ret < 0)
+ return ret;
priv->clk = clock;