diff options
| author | Vasily Khoruzhick <anarsoul@gmail.com> | 2023-03-07 21:16:10 -0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-03-19 14:12:00 +0800 |
| commit | 4340771323fc8cc9eee5508ffabbd48d0d83c27a (patch) | |
| tree | bca006bab50ccb0c42ea64c1e29c5af9f974f7f9 /drivers/clk | |
| parent | 981f0545d328b4b757c02465792b499c94bcbc00 (diff) | |
clk: rockchip: rk3568: add stubs for CLK_PCIEPHY_REF clocks
Device tree contains assigned-clock-rates property for these,
but default value will work just fine
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3568.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 253b69504f..1c6adc56f9 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -425,6 +425,9 @@ static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate) case PCLK_PMU: ret = rk3568_pmu_set_pmuclk(priv, rate); break; + case CLK_PCIEPHY0_REF: + case CLK_PCIEPHY1_REF: + return 0; default: return -ENOENT; } |