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authorAndre Przywara <andre.przywara@arm.com>2019-01-29 15:54:09 +0000
committerJagan Teki <jagan@amarulasolutions.com>2019-01-29 23:30:11 +0530
commitbb3e5aa2896d69a6fe86861004d7d4e33824efbe (patch)
tree8f38de7357c03681bc0309bd76ab52fe00e02e06 /drivers/clk/sunxi/clk_h3.c
parent1659156c74fb575d851fc1f43818d232712e776b (diff)
sunxi: clk: add MMC gates/resets
Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
Diffstat (limited to 'drivers/clk/sunxi/clk_h3.c')
-rw-r--r--drivers/clk/sunxi/clk_h3.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f82949b3b6..416aec2b89 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -13,6 +13,9 @@
#include <dt-bindings/reset/sun8i-h3-ccu.h>
static struct ccu_clk_gate h3_gates[] = {
+ [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
+ [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
+ [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
[CLK_BUS_OTG] = GATE(0x060, BIT(23)),
[CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
[CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
@@ -44,6 +47,9 @@ static struct ccu_reset h3_resets[] = {
[RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
[RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
+ [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
+ [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
+ [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
[RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),