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| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2019-03-18 05:11:42 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-03-25 20:26:53 +0100 |
| commit | 45b01b462feedaecb28c3407a438a245c73fe6d0 (patch) | |
| tree | 3f329dc38d77ea78716f222e40f7e5d3402736cb /drivers/clk/sunxi/clk_a80.c | |
| parent | c49d0ac38a76c39f9556638bc9128b0969cb1536 (diff) | |
clk: renesas: Fix SDH clock divider decoding on Gen2
The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'drivers/clk/sunxi/clk_a80.c')
0 files changed, 0 insertions, 0 deletions