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authorKever Yang <kever.yang@rock-chips.com>2017-09-28 18:24:03 +0800
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>2017-10-01 00:33:32 +0200
commitf3f6591ca39325f34ef3ec3600be2e493b3a0327 (patch)
tree429611f8814f887fe73132ab537d99c0d9c69b9b /drivers/clk/rockchip
parent5d62aba4e3acda5b0cb4dd7e45b3ec05c76e6d70 (diff)
rockchip: rk322x: fix pd_bus hclk/pclk
The pd_bus hclk/pclk source is pd_bus aclk, not the PLL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk_rk322x.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
index 6334e6293f..e87267d239 100644
--- a/drivers/clk/rockchip/clk_rk322x.c
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -117,16 +117,16 @@ static void rkclk_init(struct rk322x_cru *cru)
pclk_div << CORE_PERI_DIV_SHIFT);
/*
- * select apll as pd_bus bus clock source and
+ * select gpll as pd_bus bus clock source and
* set up dependent divisors for PCLK/HCLK and ACLK clocks.
*/
aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
- pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
+ pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
- hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
+ hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
rk_clrsetreg(&cru->cru_clksel_con[0],