diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2017-07-27 12:54:02 +0800 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-08-13 17:15:09 +0200 |
| commit | 217273cd441fe3d00a1bdad143dcb656854963f9 (patch) | |
| tree | 84b0975bed28db6f6f01bcf59d7d42cd23261e7d /drivers/clk/rockchip/clk_rk3288.c | |
| parent | 3a94d75d0e2a3b2519de51dfa1f369d976d9cccc (diff) | |
rockchip: clk: remove RATE_TO_DIV
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'drivers/clk/rockchip/clk_rk3288.c')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3288.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index adb4e1cd9d..478195b10b 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -118,9 +118,6 @@ enum { SOCSTS_NPLL_LOCK = 1 << 9, }; -#define RATE_TO_DIV(input_rate, output_rate) \ - ((input_rate) / (output_rate) - 1); - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) #define PLL_DIVISORS(hz, _nr, _no) {\ @@ -535,6 +532,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, if (src_clk_div > 0x3f) { src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); + assert(src_clk_div < 0x40); mux = EMMC_PLL_SELECT_24MHZ; assert((int)EMMC_PLL_SELECT_24MHZ == (int)MMC0_PLL_SELECT_24MHZ); @@ -608,7 +606,8 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, int src_clk_div; debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); - src_clk_div = RATE_TO_DIV(gclk_rate, freq); + src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; + assert(src_clk_div < 128); switch (periph) { case SCLK_SPI0: rk_clrsetreg(&cru->cru_clksel_con[25], |