diff options
| author | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-08-14 10:40:01 -0400 |
| commit | c1b62ba9ca0e41fdd548cb3bb9af3b3f90d4a393 (patch) | |
| tree | 7e653a1823011bfb075540428bfdab96707f1517 /drivers/clk/rockchip/clk_rk3288.c | |
| parent | bc5d0384458466ed5b3608d326eec03cd4f13016 (diff) | |
| parent | 217273cd441fe3d00a1bdad143dcb656854963f9 (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
Diffstat (limited to 'drivers/clk/rockchip/clk_rk3288.c')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3288.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 792ee76509f..478195b10b0 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -118,9 +118,6 @@ enum { SOCSTS_NPLL_LOCK = 1 << 9, }; -#define RATE_TO_DIV(input_rate, output_rate) \ - ((input_rate) / (output_rate) - 1); - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) #define PLL_DIVISORS(hz, _nr, _no) {\ @@ -530,10 +527,12 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate, int mux; debug("%s: gclk_rate=%u\n", __func__, gclk_rate); - src_clk_div = RATE_TO_DIV(gclk_rate, freq); + /* mmc clock default div 2 internal, need provide double in cru */ + src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); if (src_clk_div > 0x3f) { - src_clk_div = RATE_TO_DIV(OSC_HZ, freq); + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq); + assert(src_clk_div < 0x40); mux = EMMC_PLL_SELECT_24MHZ; assert((int)EMMC_PLL_SELECT_24MHZ == (int)MMC0_PLL_SELECT_24MHZ); @@ -607,7 +606,8 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate, int src_clk_div; debug("%s: clk_general_rate=%u\n", __func__, gclk_rate); - src_clk_div = RATE_TO_DIV(gclk_rate, freq); + src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; + assert(src_clk_div < 128); switch (periph) { case SCLK_SPI0: rk_clrsetreg(&cru->cru_clksel_con[25], |