clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()

CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC)
requires a different setting procedure. Make struct cpg_mssr_info
accessible to handle the clock setting in that case.

Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index bed2a16448..0cf80a9866 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -132,7 +132,8 @@ int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
 	return 0;
 }
 
-int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
+int renesas_clk_endisable(struct clk *clk, void __iomem *base,
+			  struct cpg_mssr_info *info, bool enable)
 {
 	const unsigned long clkid = clk->id & 0xffff;
 	const unsigned int reg = clkid / 100;