diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2022-09-09 19:59:59 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-09-23 15:09:16 -0400 |
| commit | 7fb33e9aea514cfd873d8005954108a482e9e693 (patch) | |
| tree | c940be0ad748c90af19c5c75772bc8eaf9d51c0e /drivers/clk/mediatek/clk-mtk.c | |
| parent | 59acdf8afe4a5c676f8b6ed7af48821980a2bda5 (diff) | |
clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock
The mtk clock framework in u-boot uses array index for searching clock
parent (kernel uses strings for search), so we need to specify a special
clock with ID=0 for CLK_XTAL in u-boot.
In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we
expected.
However for newer chips, they may have some clocks with ID=0 not
representing the xtal clock and still needs mtk_topckgen_get_mux_rate be
called. Current logic will make entire clock driver not working.
This patch adds a flag to indicate that whether a clock driver needs clocks
with ID=0 to call mtk_topckgen_get_mux_rate.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers/clk/mediatek/clk-mtk.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d43b8a0648c..7d145f4975a 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -319,7 +319,9 @@ static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off) index &= mux->mux_mask << mux->mux_shift; index = index >> mux->mux_shift; - if (mux->parent[index]) + if (mux->parent[index] > 0 || + (mux->parent[index] == CLK_XTAL && + priv->tree->flags & CLK_BYPASS_XTAL)) return mtk_clk_find_parent_rate(clk, mux->parent[index], NULL); |