diff options
| author | Teo Hall <teo.hall@nxp.com> | 2020-02-06 08:57:33 -0600 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2022-04-06 18:03:30 +0800 |
| commit | b0e655444d97a303e3eb555a9a1fde9723506f7f (patch) | |
| tree | b2563e4e731b45dae70b95fd317257bc1ebbd916 /drivers/clk/imx/clk-imx8qxp.c | |
| parent | b809a962a85b3f1824306a2c2abedde323219e30 (diff) | |
MLK-23279-2 imx: Add support for i.MX8DXL SoC
Add clocks required for new i.MX8DXL SoC. Since most of clocks are
same as iMX8QXP, share the same driver but with iMX8DXL new clocks added.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Teo Hall <teo.hall@nxp.com>
(cherry picked from commit f9c23b2df504c5db5f8f4567ee4c92f2439308fc)
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit dc7b8a6b97258e7a46a014e5b866cac55ad617f7)
(cherry picked from commit f4ce88dfe557dc87f3a107b32b9b6126f58160f7)
(cherry picked from commit eddd8eb01a307fa840a5a7a22bf6bd4e52330450)
Diffstat (limited to 'drivers/clk/imx/clk-imx8qxp.c')
| -rw-r--r-- | drivers/clk/imx/clk-imx8qxp.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index d78909a917..63401b466f 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -35,7 +35,9 @@ static struct imx8_clks imx8qxp_clks[] = { CLK_4( IMX8QXP_SDHC0_DIV, "SDHC0_DIV", SC_R_SDHC_0, SC_PM_CLK_PER ), CLK_4( IMX8QXP_SDHC1_DIV, "SDHC1_DIV", SC_R_SDHC_1, SC_PM_CLK_PER ), CLK_4( IMX8QXP_SDHC2_DIV, "SDHC2_DIV", SC_R_SDHC_2, SC_PM_CLK_PER ), +#if !defined(CONFIG_IMX8DXL) CLK_4( IMX8QXP_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_R_ENET_0, SC_PM_CLK_PER ), +#endif CLK_4( IMX8QXP_ENET0_RGMII_DIV, "ENET0_RGMII_DIV", SC_R_ENET_0, SC_PM_CLK_MISC0 ), CLK_4( IMX8QXP_ENET1_ROOT_DIV, "ENET1_ROOT_DIV", SC_R_ENET_1, SC_PM_CLK_PER ), CLK_4( IMX8QXP_ENET1_RGMII_DIV, "ENET1_RGMII_DIV", SC_R_ENET_1, SC_PM_CLK_MISC0 ), @@ -57,6 +59,9 @@ static struct imx8_fixed_clks imx8qxp_fixed_clks[] = { CLK_3( IMX8QXP_LSIO_MEM_CLK, "LSIO_MEM_CLK", SC_200MHZ ), CLK_3( IMX8QXP_HSIO_PER_CLK, "HSIO_CLK", SC_133MHZ ), CLK_3( IMX8QXP_HSIO_AXI_CLK, "HSIO_AXI", SC_400MHZ ), +#if defined(CONFIG_IMX8DXL) + CLK_3( IMX8QXP_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_250MHZ ), +#endif }; static struct imx8_gpr_clks imx8qxp_gpr_clks[] = { @@ -125,6 +130,15 @@ static struct imx8_lpcg_clks imx8qxp_lpcg_clks[] = { CLK_5( IMX8QXP_ENET1_RGMII_TX_CLK, "ENET1_RGMII_TX", 12, ENET_1_LPCG, IMX8QXP_ENET1_RMII_TX_SEL ), CLK_5( IMX8QXP_ENET1_RMII_RX_CLK, "ENET1_RMII_RX", 0, ENET_1_LPCG + 0x4, IMX8QXP_ENET1_RGMII_DIV ), +#if defined(CONFIG_IMX8DXL) + CLK_5( IMX8DXL_EQOS_MEM_CLK, "EQOS_MEM_CLK", 8, ENET_1_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8DXL_EQOS_ACLK, "EQOS_ACLK", 16, ENET_1_LPCG, IMX8DXL_EQOS_MEM_CLK ), + CLK_5( IMX8DXL_EQOS_CSR_CLK, "EQOS_CSR_CLK", 24, ENET_1_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8DXL_EQOS_CLK, "EQOS_CLK", 20, ENET_1_LPCG, IMX8QXP_ENET1_ROOT_DIV ), + CLK_5( IMX8DXL_EQOS_PTP_CLK_S, "EQOS_PTP_S", 8, ENET_1_LPCG, IMX8QXP_ENET0_ROOT_DIV ), + CLK_5( IMX8DXL_EQOS_PTP_CLK, "EQOS_PTP", 0, ENET_1_LPCG, IMX8DXL_EQOS_PTP_CLK_S ), +#endif + CLK_5( IMX8QXP_LSIO_FSPI0_IPG_S_CLK, "FSPI0_IPG_S", 0x18, FSPI_0_LPCG, IMX8QXP_LSIO_BUS_CLK ), CLK_5( IMX8QXP_LSIO_FSPI0_IPG_CLK, "FSPI0_IPG", 0x14, FSPI_0_LPCG, IMX8QXP_LSIO_FSPI0_IPG_S_CLK ), CLK_5( IMX8QXP_LSIO_FSPI0_HCLK, "FSPI0_HCLK", 0x10, FSPI_0_LPCG, IMX8QXP_LSIO_MEM_CLK ), |