Merge tag 'lf-5.15.71-2.2.2' into toradex_imx_lf_v2022.04

This pulls in the following commits:
git log --oneline --no-merges  ^HEAD lf-5.15.71-2.2.2

14b6c8f3e3b MA-20886 imx8ulp: Boot from recovery mode when pressing key
62ad7799b6c LF-7602: Device tree fixup based on compatible string
b35420da607 crypto: fsl_hash: Remove unnecessary alignment check in caam_hash()
918dbf78bbb MA-20872 Revert "MA-18775 system will hang about 3s when boot up kernel"
ed2c3cbd6ac MA-20814 add fastboot command to erase u-boot env
a6762e28bf0 LF-6627: nand drvier fixups in sdboot on ls1043ardb-pd
d23cfa09767 LFU-426: qspihdr: Coverity Issue: unchecked return value
413b08f841f MLK-25850: imx8dxl_ddr3l_evk: change the default fdt file name
e91a047f54f LF-7382: fastboot: improve emmc write speed
205680f9f4b LFU-428 imx8ulp: Add warning for CAAM non-secure state failure
f405551dcc1 LF-7369-2 clk: imx93: update LPCG control API
676831be672 LF-7369-1 clk: imx: implement a clock gate driver for i.MX93
94c5bb2eb83 MA-20507-7 trusty: fix dereference null return value
6933487b4df LFU-427 imx93: Print ELE FW version
15b1ebb00cc LFU-393 imx93: Add reset cause print
f3b75e3317d LF-7332 imx8/ahab: sha256: enable image verification using ARMv8 crypto extention
330e2634143 LFU-423: usb: cdns3: gadget: Avoid using usb_ss after null check
58ba744cbad MLK-26034 imx6: Disable LCDIF clock before jumping to kernel
ae396d343a3 LF-6627: nand drvier fixups in nandboot on ls1043ardb-pd
0a99627b60e LFU-422-2 imx8ulp_evk: Enable the GD25LX256E support
c6c06de038f LFU-422-1 mtd: spi-nor: Add GigaDevice GD25LX256E NOR flash
032fab5e127 LFU-421 imx93_evk: Add imx93 low drive mode support on 11x11 EVK
d9f477625d3 LF-7332 armv8: SHA-256 using ARMv8 Crypto Extensions
53689e4f7db MA-20667 set metadata partition of type f2fs
f824cd01955 LFU-415 net: fec_mxc: Skip recv packet process when fec is halted
4e7c44e1f33 LFU-419 arm: dts: imx8mp: fix flexspi nand reg
957bdd9c925 LFU-418 imx8ulp: upower_hal: make code cleaner
361b23b98ed Revert "MLK-25478-1 efi: add Platform-Reset-Attack variables"
e1ed0611b5e Revert "MLK-25478-2 efi: clean memory and reset MemoryOverwriteRequestControl"
4998fef38a5 Revert "MLK-25478-3 workaround: disable verify time of signer and signee."
320096439b6 MA-20738 imx8ulp: bumps CONFIG_LMB_MAX_REGIONS
c244bdfd76c LFU-417-2 imx93_evk/qsb: Enable DDR inline ECC feature
026521c7d65 LFU-417-1 ddr: imx: imx9: Add DDR inline ECC support
a555a21be69 LFU-413 imx8ulp_evk: Remove CONFIG_BOOTDELAY=0 from ND defconfig
aaead5a2b8d LFU-416 imx: cmd_dek: Fix build warning in blob_encap_dek
933a3b25fe3 LF-7234 enable CONFIG_CMD_CRC32 and CONFIG_CRC32_VERIFY
97fc905e7f7 LFU-409: imx8dxl: fix the i.MX8DXL ddr3l NAND DQS iomux setting
aa4ebb66199 LFU-414 imx8ulp: clock: Update clocks to meet max rate restrictions
63d0579f397 LFU-410 imx: ele_ahab: Add ahab_sec_fuse_prog command
266dddae454 LFU-412 configs: imx93_evk: shrink mem= for jailhouse
5703d3ae37e LFU-411 imx8ulp: Always enable MIPI_DSI power switch
32965eb52f7 LFU-392 imx8ulp: upower: replace magic number with macro
beb5e5e3303 MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default
bb45dd592db LFU-408 imx93evk: config the pmic standby voltage for buck1
25e38cb4762 LFU-407-02 ddr: imx9: Change the saved ddr data base to 0x2051c000
a8fef10ab92 LFU-407-01 configs: imx93: Update spl stack & bss base address
8731024fe7e LFU-406 mx6ul/mx6ulz: Fix build break caused by RNG patch
a95afe08769 LF-7238 imx9: soc: Remove OPTEE memory from DRAM bank and MMU
19c3fdebf8d LFU-403-4 imx93_evk/qsb: Enable TMU sensor driver
e1703ec06a4 LFU-403-3 iMX93: soc: print current CPU temperature
050a94e6365 LFU-403-2 DTS: imx93: Update TMU node to sync with kernel
91e711a565c LFU-403-1 thermal: imx_tmu: Update TMU driver to support iMX93
78749666dd3 LFU-402-3 imx93_evk/qsb: Use API to set max ARM clock
401b9824f92 LFU-402-2 iMX93: clock: Add API to set max ARM core clock
e4722baa5af LFU-402-1 iMX93: soc: Get market segment and speed grading
432a4af9608 LFU-400 imx8ulp: clock: Clear dividers in PLL3DIV_PFD registers
53f06207782 LFU-399 imx8ulp: Reconfigure MRC3 for SRAM0 access
48a2221acc9 LFU-395 imx93: Add fused parts support
d8760a74793 LFU-398-7 imx93_9x9_qsb: Enable Flexspi NOR support
1f500a59670 LFU-398-6 imx93_qsb: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
ba4f72198f5 LFU-398-5 DTS: imx93-9x9-qsb: Add flexspi NOR nodes and pinctrl
d9f563336f7 LFU-398-4 imx93_11x11_evk: Enable Flexspi NOR support
c56f2132d53 LFU-398-3 imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
b6cbe6b1416 LFU-398-2 DTS: imx93-11x11-evk: Enable and update flexspi NOR
c45c4fb791b LFU-398-1 DTS: imx93: Update flexspi node in DTSi
fab973fe1df LFU-397 imx8m: clock: not configure reserved SRC register
4881ba99fa4 LFU-396-7 imx93_9x9_qsp_defconfig: support splash screen
60e0e629f99 LFU-396-6 arm: dts: add imx93 9x9 ontat panel dts
fffc330cf1a LFU-396-5 imx9: clock: add 300MHz fracn pll table
ef6a3d9cc38 LFU-396-4 video: nxp: imx: add Add i.MX93 parallel display format encoder driver
5f414738a5f LFU-396-3 video: nxp: imx_lcdifv3: support VSYNC/HSYNC active low
21eb66fe1f8 LFU-396-2 video: nxp: imx: dsi: force DISPLAY_FLAGS_HSYNC_HIGH & DISPLAY_FLAGS_VSYNC_HIGH
88132ed0b4e LFU-396-1 video: simple_panel: make backlight optional
65287dc074d LF-7055: video: imx: Add set_parent calls to LVDS initialization
167f65006fb MLK-26021 imx93: add 9x9 qsb lpddr4 board
0a6297a290e MA-20677 imx8ulp: android: enable CONFIG_AHAB_BOOT by default
8789f3ca3e4 PLATSEC-1781-2 MX6: Device tree fix-up
60555c4a445 PLATSEC-1781-1 mx6ull:Add config CONFIG_OF_SYSTEM_SETUP
48b1d6e34fd MA-20149 set fs type of android partitions
9710cc4840e LFOPTEE-177 imx93evk: enable cmd_dek command
f0721d67f03 LFOPTEE-177 imx8ulp: enable cmd_dek command
bf07f5166bf LFOPTEE-177 imx: cmd_dek: add ELE DEK Blob generation support
6de56c3f629 LFOPTEE-177 s400_api: add DEK Blob generation

Conflicts:
	drivers/crypto/fsl/fsl_hash.c
	commit 41b2182af73 ("crypto: fsl_hash: Remove unnecessary
	alignment check in caam_hash()")
	Both NXP and TXD branch did cherry-picking that commit, but NXP
	additionally removed a debug print (not present in master)
	while the TDX branch did not. Resolved by doing it the NXP way.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

1 files changed, 146 insertions, 0 deletions

diff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c
new file mode 100644
index 0000000000..7b43f18e6e
--- /dev/null
+++ b/drivers/clk/imx/clk-gate-93.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Author: Alice Guo <alice.guo@nxp.com>
+ */
+
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <linux/bug.h>
+#include <linux/clk-provider.h>
+
+#include "clk.h"
+
+#define LPCG_DIRECT		0x0
+#define LPCG_LPM_CUR		0x1c
+#define LPM_SETTING_OFF		0x0
+#define LPM_SETTING_ON		0x4
+#define LPCG_AUTHEN		0x30
+#define WHITE_LIST_DM0		16
+#define DOMAIN_ID_A55		3
+#define TZ_NS			BIT(9)
+#define CPULPM_MOD		BIT(2)
+
+struct imx93_clk_gate {
+	struct clk	clk;
+	void __iomem	*reg_base;
+	u8		lpcg_on_offset;
+	u8		lpcg_on_ctrl;
+	u8		lpcg_on_mask;
+	ulong		flags;
+};
+
+#define to_imx93_clk_gate(_clk) container_of(_clk, struct imx93_clk_gate, clk)
+
+static bool imx93_clk_gate_check_authen(void __iomem *reg_base)
+{
+	u32 authen;
+
+	authen = readl(reg_base + LPCG_AUTHEN);
+	if (!(authen & TZ_NS) || !(authen & BIT(WHITE_LIST_DM0 + DOMAIN_ID_A55)))
+		return false;
+
+	return true;
+}
+
+static void imx93_clk_gate_ctrl_hw(struct clk *clk, bool enable)
+{
+	struct imx93_clk_gate *gate = to_imx93_clk_gate(clk);
+	u32 v;
+
+	v = readl(gate->reg_base + LPCG_AUTHEN);
+	if (v & CPULPM_MOD) {
+		v = enable ? LPM_SETTING_ON : LPM_SETTING_OFF;
+		writel(v, gate->reg_base + LPCG_LPM_CUR);
+	} else {
+		v = readl(gate->reg_base + LPCG_DIRECT);
+		v &= ~(gate->lpcg_on_mask << gate->lpcg_on_offset);
+		if (enable)
+			v |= (gate->lpcg_on_ctrl & gate->lpcg_on_mask) << gate->lpcg_on_offset;
+		writel(v, gate->reg_base + LPCG_DIRECT);
+	}
+}
+
+static int imx93_clk_gate_enable(struct clk *clk)
+{
+	struct imx93_clk_gate *gate = to_imx93_clk_gate(clk);
+
+	if (!imx93_clk_gate_check_authen(gate->reg_base))
+		return -EINVAL;
+
+	imx93_clk_gate_ctrl_hw(clk, true);
+
+	return 0;
+}
+
+static int imx93_clk_gate_disable(struct clk *clk)
+{
+	struct imx93_clk_gate *gate = to_imx93_clk_gate(clk);
+
+	if (!imx93_clk_gate_check_authen(gate->reg_base))
+		return -EINVAL;
+
+	imx93_clk_gate_ctrl_hw(clk, false);
+
+	return 0;
+}
+
+static ulong imx93_clk_gate_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk *parent = clk_get_parent(clk);
+
+	if (parent)
+		return clk_set_rate(parent, rate);
+
+	return -ENODEV;
+}
+
+static const struct clk_ops imx93_clk_gate_ops = {
+	.set_rate = imx93_clk_gate_set_rate,
+	.enable = imx93_clk_gate_enable,
+	.disable = imx93_clk_gate_disable,
+	.get_rate = clk_generic_get_rate,
+};
+
+static struct clk *register_clk_gate(const char *name, const char *parent_name,
+				     void __iomem *reg_base, u8 lpcg_on_offset,
+				     u8 lpcg_on_ctrl, u8 lpcg_on_mask, ulong flags)
+{
+	struct imx93_clk_gate *gate;
+	int ret;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return ERR_PTR(-ENOMEM);
+
+	gate->reg_base = reg_base;
+	gate->lpcg_on_offset = lpcg_on_offset;
+	gate->lpcg_on_ctrl = lpcg_on_ctrl;
+	gate->lpcg_on_mask = lpcg_on_mask;
+	gate->flags = flags;
+
+	ret = clk_register(&gate->clk, "imx93_clk_gate", name, parent_name);
+	if (ret) {
+		kfree(gate);
+		return ERR_PTR(ret);
+	}
+
+	return &gate->clk;
+}
+
+struct clk *clk_register_imx93_clk_gate(const char *name, const char *parent_name,
+					void __iomem *reg_base, u8 lpcg_on_offset,
+					ulong flags)
+{
+	return register_clk_gate(name, parent_name, reg_base, lpcg_on_offset, 1,
+				 1, flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
+}
+
+U_BOOT_DRIVER(imx93_clk_gate) = {
+	.name = "imx93_clk_gate",
+	.id = UCLASS_CLK,
+	.ops = &imx93_clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};