diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2018-02-08 17:20:45 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-03-13 21:45:37 -0400 |
| commit | aa230be4bf69956ed8fe09cdf9c5fada1750b251 (patch) | |
| tree | 6ac02f0a1d4c1b92a16b2aa9c7eb4f2b7273b8e7 /drivers/clk/clk_stm32f.c | |
| parent | 167f2c90f6b4b0561db610fb24f9a5519e0baefd (diff) | |
clk: clk_stm32f: Fix stm32_clk_get_rate()
Wrong parameter was passed to stm32_clk_pll48clk_rate().
sysclk (PLL_p output value) was passed instead of VCO value.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'drivers/clk/clk_stm32f.c')
| -rw-r--r-- | drivers/clk/clk_stm32f.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index f1f02995d9..41d8b5e5c8 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -230,7 +230,7 @@ static int configure_clocks(struct udevice *dev) } static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, - u32 sysclk) + u32 vco) { struct stm32_rcc_regs *regs = priv->base; u16 pllq, pllm, pllsain, pllsaip; @@ -254,7 +254,7 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, return ((priv->hse_rate / pllm) * pllsain) / pllsaip; } /* PLL48CLK is selected from PLLQ */ - return sysclk / pllq; + return vco / pllq; } static bool stm32_get_timpre(struct stm32_clk *priv) @@ -337,6 +337,7 @@ static ulong stm32_clk_get_rate(struct clk *clk) struct stm32_clk *priv = dev_get_priv(clk->dev); struct stm32_rcc_regs *regs = priv->base; u32 sysclk = 0; + u32 vco; u16 pllm, plln, pllp; if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == @@ -346,7 +347,8 @@ static ulong stm32_clk_get_rate(struct clk *clk) >> RCC_PLLCFGR_PLLN_SHIFT); pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); - sysclk = ((priv->hse_rate / pllm) * plln) / pllp; + vco = (priv->hse_rate / pllm) * plln; + sysclk = vco / pllp; } else { return -EINVAL; } @@ -388,14 +390,14 @@ static ulong stm32_clk_get_rate(struct clk *clk) /* System clock is selected as SDMMC1 clock */ return sysclk; else - return stm32_clk_pll48clk_rate(priv, sysclk); + return stm32_clk_pll48clk_rate(priv, vco); break; case STM32F7_APB2_CLOCK(SDMMC2): if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) /* System clock is selected as SDMMC2 clock */ return sysclk; else - return stm32_clk_pll48clk_rate(priv, sysclk); + return stm32_clk_pll48clk_rate(priv, vco); break; /* For timer clock, an additionnal prescaler is used*/ |