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| author | Hai Pham <hai.pham.ud@renesas.com> | 2020-05-22 10:39:04 +0700 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-05-21 15:00:17 +0200 |
| commit | f7f8d473170dd7bd79bf034accf65a10b2f3edf6 (patch) | |
| tree | 64111125cf62505dfba48c12a8a8d40e3f751aa1 /drivers/clk/clk.c | |
| parent | e9354091995c9129f1ebf7a568a42e17c2b2f96e (diff) | |
clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC)
requires a different setting procedure. Make struct cpg_mssr_info
accessible to handle the clock setting in that case.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Diffstat (limited to 'drivers/clk/clk.c')
0 files changed, 0 insertions, 0 deletions