summaryrefslogtreecommitdiff
path: root/drivers/cache
diff options
context:
space:
mode:
authorLey Foon Tan <ley.foon.tan@intel.com>2020-05-04 18:41:55 +0800
committerTom Rini <trini@konsulko.com>2020-05-06 15:12:48 -0400
commit653f7c44677cd13bb106673bb7c46542e217fa13 (patch)
tree9acf4fc82e747b1788bec31a07e6568e734a2f79 /drivers/cache
parent15c160301cf4761d45e09808f9d818525425901b (diff)
cache: l2x0: Fix missing write to Auxiliary Control Register
In commit f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") we removed writel to regs->pl310_aux_ctrl by accident. This commit restores it back. Fixes: f62782fb2999 ("cache: l2x0: Fix write to incorrect shared-override bit") Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'drivers/cache')
-rw-r--r--drivers/cache/cache-l2x0.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c
index 226824c283..a1556fbf17 100644
--- a/drivers/cache/cache-l2x0.c
+++ b/drivers/cache/cache-l2x0.c
@@ -36,6 +36,8 @@ static void l2c310_of_parse_and_init(struct udevice *dev)
if (dev_read_bool(dev, "arm,shared-override"))
saved_reg |= L310_SHARED_ATT_OVERRIDE_ENABLE;
+ writel(saved_reg, &regs->pl310_aux_ctrl);
+
saved_reg = readl(&regs->pl310_tag_latency_ctrl);
if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3))
saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) |