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authorYork Sun <yorksun@freescale.com>2012-10-08 07:44:27 +0000
committerAndy Fleming <afleming@freescale.com>2012-10-22 14:31:30 -0500
commit89b78095681fd3dfd359082ba62d80551a114ab0 (patch)
tree4f994670e33eb536a1263aefa46664c951dc0191 /doc
parenta1d558a20f1eaeae9927abc4e0978725d33bae53 (diff)
powerpc/mpc8xxx: Add auto select bank interleaving mode
Based on populated DIMMs, automatically select from cs0_cs1_cs2_cs3 or cs0_cs1 interleaving, or non-interleaving if not available. Fix the message of interleaving disabled if controller interleaving is enabled but DIMMs don't support it. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/README.fsl-ddr5
1 files changed, 5 insertions, 0 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index f94b56f628c..3992640ba30 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -103,6 +103,11 @@ The ways to configure the ddr interleaving mode
# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
+ # bank(chip-select) interleaving (auto)
+ setenv hwconfig "fsl_ddr:bank_intlv=auto"
+ This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
+ on DIMMs.
+
Memory controller address hashing
==================================
If the DDR controller supports address hashing, it can be enabled by hwconfig.