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authoryork <yorksun@freescale.com>2010-07-02 22:25:54 +0000
committerKumar Gala <galak@kernel.crashing.org>2010-07-26 13:16:09 -0500
commit7fd101c97b58dab7b0bd87f30c3dedb0db21d15f (patch)
treefe0f75ff8b46b1bc0367f6c600418a596eaee446 /doc
parent5800e7ab32c200836e81ab2384817d93105561c5 (diff)
powerpc/8xxx: Enabled address hashing for 85xx
For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/README.fsl-ddr15
1 files changed, 13 insertions, 2 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 8c37bbead1f..e108a0d50c9 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -71,5 +71,16 @@ The ways to configure the ddr interleaving mode
# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
- The above memory controller interleaving and bank interleaving can be mixed. The syntax is
- setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"
+Memory controller address hashing
+==================================
+If the DDR controller supports address hashing, it can be enabled by hwconfig.
+
+Syntax is:
+hwconfig=fsl_ddr:addr_hash=true
+
+Combination of hwconfig
+=======================
+Hwconfig can be combined with multiple parameters, for example, on a supported
+platform
+
+hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3