diff options
| author | Marek Vasut <marex@denx.de> | 2014-10-22 21:56:03 +0200 |
|---|---|---|
| committer | Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> | 2014-10-27 22:37:03 +0530 |
| commit | df155672ff262dd779ef12c04d9fc1911b778990 (patch) | |
| tree | a4504d4a720f93744d28aefc170e99138e8b11db /doc | |
| parent | bc76b821f05fa4cdfca406cba975657de7a8e9f8 (diff) | |
spi: altera: Add short note about EPCS/EPCQx1
Add short documentation-alike note on how to use the Altera SPI
driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V
into doc/SPI/README.altera_spi
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/SPI/README.altera_spi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/doc/SPI/README.altera_spi b/doc/SPI/README.altera_spi new file mode 100644 index 00000000000..b07449f80d6 --- /dev/null +++ b/doc/SPI/README.altera_spi @@ -0,0 +1,6 @@ +SoCFPGA EPCS/EPCQx1 mini howto: +- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild +- The controller base address is the "Base" in QSys + 0x400 +- Set MSEL[4:0]=10010 (AS Standard) +- Load the bitstream into FPGA, enable bridges +- Only then will the driver work |