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authorManorit Chawdhry <m-chawdhry@ti.com>2023-04-14 13:46:02 +0530
committerUdit Kumar <u-kumar1@ti.com>2023-04-16 09:25:03 +0530
commit6c732bda5d9c43ea7fb03281b6d594c19a045c45 (patch)
treee643a183249a8cda51f752159039254c0b2aec90 /doc
parent356722489b6004b75ab075bd5a5da530bcdb84fe (diff)
Kconfig: j721e: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region
In non-combined boot flow for K3, all the firewalls are locked by default until sysfw comes up. Rom configures some of the firewall for its usage along with the SRAM for R5 but the PSRAM region is still locked. The K3 MCU Scratchpad for j721e was set to a PSRAM region triggering the firewall exception before sysfw came up. The exception started happening after adding multi dtb support that accesses the scratchpad for reading EEPROM contents. The commit changes R5 MCU scratchpad for j721e to an SRAM region. Old Map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c40000 (approx) │ STACK │ ├─────────────────────────────────────┤ 0x41c85b20 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c85bfc │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41cf5bfc) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) New Map: ┌─────────────────────────────────────┐ 0x41c00000 │ SPL │ ├─────────────────────────────────────┤ 0x41c40000 (approx) │ EMPTY │ ├─────────────────────────────────────┤ 0x41c81920 │ STACK │ │ SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000 │ ├─────────────────────────────────────┤ 0x41c85920 │ Global data │ │ sizeof(struct global_data) = 0xd8 │ ├─────────────────────────────────────┤ gd->malloc_base = 0x41c859f0 │ HEAP │ │ CONFIG_SYS_MALLOC_F_LEN = 0x70000 │ ├─────────────────────────────────────┤ CONFIG_SPL_BSS_START_ADDR │ SPL BSS │ (0x41cf59f0) │ CONFIG_SPL_BSS_MAX_SIZE = 0xA000 │ ├─────────────────────────────────────┤ 0x41cff9fc │ NEW MCU SCRATCHPAD │ │ SYS_K3_MCU_SCRATCHPAD_SIZE = 0x200 │ └─────────────────────────────────────┘ CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX (0x41cffbfc) Fixes: ab977c8b91b4 ("configs: j721s2_evm_r5: Enable support for building multiple dtbs into FIT") Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com> [n-francis@ti.com: SRAM allocation addressing diagram] Signed-off-by: Neha Francis <n-francis@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Kamlesh Gurudasani <kamlesh@ti.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/board/ti/j721e_evm.rst43
1 files changed, 43 insertions, 0 deletions
diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst
index e898601c41..feaa2da5e9 100644
--- a/doc/board/ti/j721e_evm.rst
+++ b/doc/board/ti/j721e_evm.rst
@@ -268,6 +268,49 @@ Image formats:
| +-------------------+ |
+-----------------------+
+R5 Memory Map:
+--------------
+
+.. list-table::
+ :widths: 16 16 16
+ :header-rows: 1
+
+ * - Region
+ - Start Address
+ - End Address
+
+ * - SPL
+ - 0x41c00000
+ - 0x41c40000
+
+ * - EMPTY
+ - 0x41c40000
+ - 0x41c81920
+
+ * - STACK
+ - 0x41c85920
+ - 0x41c81920
+
+ * - Global data
+ - 0x41c859f0
+ - 0x41c85920
+
+ * - Heap
+ - 0x41c859f0
+ - 0x41cf59f0
+
+ * - BSS
+ - 0x41cf59f0
+ - 0x41cff9f0
+
+ * - MCU Scratchpad
+ - 0x41cff9fc
+ - 0x41cffbfc
+
+ * - ROM DATA
+ - 0x41cffbfc
+ - 0x41cfffff
+
OSPI:
-----
ROM supports booting from OSPI from offset 0x0.