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authorDave Gerlach <d-gerlach@ti.com>2022-05-23 17:05:42 +0300
committerAnand Gadiyar <gadiyar@ti.com>2022-06-02 19:03:21 -0500
commit91f80b5f4257f825bfc211aad142fd14cc289e62 (patch)
treeeb39b7ba5d946dc5a8e5c3a015aee74c7a544e28 /doc
parent815467a4a81dcc736efafd6c3556495f2c903857 (diff)
dt-bindings: memory-controller: Add information about ECC bindings
commit 7b8a96e57e1db60f742184822a7d8dc508605f1f upstream Add DT binding documentation for enabling ECC in the DDR sub system present on AM64 device. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> [g-vlaev@ti.com: backport from upstream] Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
index c4cf26eaa4..686c11dd8b 100644
--- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
+++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
@@ -13,6 +13,7 @@ Required properties:
"ti,am64-ddrss" for am642
- reg-names cfg - Map the controller configuration region
ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
+ ss - Map the DDRSS configuration region
- reg: Contains the register map per reg-names.
- power-domains: Should contain two entries:
- an entry to TISCI DDR CFG device
@@ -32,6 +33,13 @@ Required properties:
- ti,pi-data: An array containing the phy independent block settings
- ti,phy-data: An array containing the ddr phy settings.
+Optional properties:
+--------------------
+- reg-names ss - Map the DDRSS configuration region
+- reg: Must add "ss" to list if the above ss region is included.
+- ti,ecc-enable: Boolean flag to enable ECC. This will reduce available DDR
+ by 1/9.
+
Example (J721E):
================