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| author | Angelo Durgehello <angelo.dureghello@timesys.com> | 2019-11-15 23:54:19 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-01-10 10:25:13 -0500 |
| commit | 05ffdc85cac85825ed0dc525ab28f4fa12a84574 (patch) | |
| tree | be8f9cf028142dfc594ca64e65382ef3a1d852df /doc | |
| parent | a7bcace28a7c966f14e2049d8a1027c9f0097593 (diff) | |
drivers: fsl_mcdmafec: conversion to dm
Full conversion to dm for all boards, legacy code removed.
Signed-off-by: Angelo Durgehello <angelo.dureghello@timesys.com>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt b/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt new file mode 100644 index 0000000000..e237825bac --- /dev/null +++ b/doc/device-tree-bindings/net/fsl,mcf-dma-fec.txt @@ -0,0 +1,35 @@ +* Freescale ColdFire DMA-FEC ethernet controller + +Required properties: +- compatible: should be "fsl,mcf-dma-fec" +- reg: address and length of the register set for the device. +- rx-task: dma channel +- tx-task: dma channel +- rx-priority: dma channel +- tx-priority: dma channel +- rx-init: dma channel +- tx-init: dma channel + +Optional properties: +- mii-base: index of FEC reg area, 0 for FEC0, 1 for FEC1 +- max-speed: max speedm Mbits/sec +- phy-addr: phy address +- timeout-loop: integer value for driver loops time out + + +Example: + +fec0: ethernet@9000 { + compatible = "fsl,mcf-dma-fec"; + reg = <0x9000 0x800>; + mii-base = <0>; + phy-addr = <0>; + timeout-loop = <5000>; + rx-task = <0>; + tx-task = <1>; + rx-piority = <6>; + tx-piority = <7>; + rx-init = <16>; + tx-init = <17>; + status = "disabled"; +}; |