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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2019-04-10 14:09:22 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@st.com> | 2019-05-23 11:38:10 +0200 |
| commit | 0cb1aa94093c22dd5b3dce32d371e154abc06ffe (patch) | |
| tree | 49ed36ed0ab1c83ab82b0aa849454638365460f0 /doc | |
| parent | c3ec370aed1d64c70578b22b18bed5c05f040962 (diff) | |
stm32mp1: ram: increase the delay after reset to 128 cycles
Component Notification DDR controller errata (3.00a):9001313030
Synchronization Time Waited After De-assertion of presetn is
128 pclk Cycles.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'doc')
0 files changed, 0 insertions, 0 deletions