diff options
| author | Bin Meng <bmeng.cn@gmail.com> | 2015-10-11 21:37:44 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-10-21 07:46:27 -0600 |
| commit | 638a05894169b07ea8f6d21b6925ca353ea6ebb7 (patch) | |
| tree | 68308063e00f4b803a07b9f55d56b2973edc2c7b /doc | |
| parent | 8b185041a9f4c30dc5edb1e04c0834e931b8633f (diff) | |
x86: Enable mrc cache for bayleybay and minnowmax
Now that we have added MRC cache for Intel FSP and BayTrail codes,
enable it for all BayTrail boards (Bayley Bay and Minnow Max).
Note it turns out that FSP for Intel Atom E6xx does not produce
the HOB for NV storage, so we don't have such functionality on
Intel Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/README.x86 | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/doc/README.x86 b/doc/README.x86 index a9d0e0fbfef..1271e5edea3 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -190,6 +190,7 @@ Offset Description Controlling config 000000 descriptor.bin Hard-coded to 0 in ifdtool 001000 me.bin Set by the descriptor 500000 <spare> +6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE 790000 vga.bin CONFIG_VGA_BIOS_ADDR 7c0000 fsp.bin CONFIG_FSP_ADDR |