Merge branch 'master' of git://git.denx.de/u-boot-spi

- SPI-NOR support

2 files changed, 0 insertions, 93 deletions

diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
deleted file mode 100644
index 6c88d65dd4..0000000000
--- a/doc/SPI/README.dual-flash
+++ /dev/null
@@ -1,92 +0,0 @@
-SPI/QSPI Dual flash connection modes:
-=====================================
-
-This describes how SPI/QSPI flash memories are connected to a given
-controller in a single chip select line.
-
-Current spi_flash framework supports, single flash memory connected
-to a given controller with single chip select line, but there are some
-hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
-connected with a single chip select line from a controller.
-
-"dual_flash" from include/spi.h describes these types of connection mode
-
-Possible connections:
---------------------
-SF_SINGLE_FLASH:
-       - single spi flash memory connected with single chip select line.
-
-  +------------+             CS         +---------------+
-  |            |----------------------->|               |
-  | Controller |         I0[3:0]        | Flash memory  |
-  | SPI/QSPI   |<======================>| (SPI/QSPI)    |
-  |            |           CLK          |               |
-  |            |----------------------->|               |
-  +------------+                        +---------------+
-
-SF_DUAL_STACKED_FLASH:
-       - dual spi/qspi flash memories are connected with a single chipselect
-         line and these two memories are operating stacked fasion with shared buses.
-       - xilinx zynq qspi controller has implemented this feature [1]
-
-  +------------+        CS             +---------------+
-  |            |---------------------->|               |
-  |            |              I0[3:0]  | Upper Flash   |
-  |            |            +=========>| memory        |
-  |            |            |     CLK  | (SPI/QSPI)    |
-  |            |            |    +---->|               |
-  | Controller |        CS  |    |     +---------------+
-  | SPI/QSPI   |------------|----|---->|               |
-  |            |    I0[3:0] |    |     | Lower Flash   |
-  |            |<===========+====|====>| memory        |
-  |            |          CLK    |     | (SPI/QSPI)    |
-  |            |-----------------+---->|               |
-  +------------+                       +---------------+
-
-       - two memory flash devices should has same hw part attributes (like size,
-         vendor..etc)
-       - Configurations:
-               on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
-               Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
-               Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
-       - Operation:
-               accessing memories serially like one after another.
-               by default, if U_PAGE is unset lower memory should accessible,
-               once user wants to access upper memory need to set U_PAGE.
-
-SPI_FLASH_CONN_DUALPARALLEL:
-	- dual spi/qspi flash memories are connected with a single chipselect
-	  line and these two memories are operating parallel with separate buses.
-	- xilinx zynq qspi controller has implemented this feature [1]
-
-  +-------------+           CS		+---------------+
-  |		|---------------------->|		|
-  | 		|        I0[3:0]	| Upper Flash	|
-  | 		|<=====================>| memory	|
-  |		|	   CLK		| (SPI/QSPI)	|
-  |		|---------------------->|		|
-  | Controller	|	    CS		+---------------+
-  | SPI/QSPI	|---------------------->|		|
-  | 		|        I0[3:0]	| Lower Flash	|
-  | 		|<=====================>| memory	|
-  |		|	   CLK		| (SPI/QSPI)	|
-  |		|---------------------->|		|
-  +-------------+			+---------------+
-
-	- two memory flash devices should has same hw part attributes (like size,
-	  vendor..etc)
-	- Configurations:
-		Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
-	- Operation:
-		Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
-		and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
-
-Note: Technically there is only one CS line from the controller, but
-zynq qspi controller has an internal hw logic to enable additional CS
-when controller is configured for dual memories.
-
-[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
-
---
-Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
-05-01-2014.
diff --git a/doc/SPI/README.ti_qspi_dra_test b/doc/SPI/README.ti_qspi_dra_test
index fe37857236..e89f53587f 100644
--- a/doc/SPI/README.ti_qspi_dra_test
+++ b/doc/SPI/README.ti_qspi_dra_test
@@ -22,7 +22,6 @@ Commands to erase/write u-boot/mlo to flash device
 --------------------------------------------------
 U-Boot# sf probe 0
 SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c000000
-SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR
 U-Boot# sf erase 0 0x10000
 SF: 65536 bytes @ 0x0 Erased: OK
 U-Boot# sf erase 0x20000 0x10000