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authorTom Rini <trini@ti.com>2012-09-25 12:23:55 -0700
committerTom Rini <trini@ti.com>2012-09-25 12:23:55 -0700
commit5675b509165b67465a20e5cf71e07f40b449ef0c (patch)
tree9886f3e8fa8734ec9f8d9cb484fcaa87ff70203f /doc
parentee1f4caaa2a3f79d692155eec8a4c7289d60e106 (diff)
parentd69dba367aed051663d0ee1ece013c8232bfa9f5 (diff)
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'doc')
-rw-r--r--doc/README.fsl-ddr36
-rw-r--r--doc/README.pblimage114
-rw-r--r--doc/README.srio-boot-corenet103
-rw-r--r--doc/README.srio-pcie-boot-corenet112
4 files changed, 260 insertions, 105 deletions
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 5e216587659..f94b56f628c 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -1,5 +1,28 @@
-
-Table of interleaving modes supported in cpu/8xxx/ddr/
+Table of interleaving 2-4 controllers
+=====================================
+ +--------------+-----------------------------------------------------------+
+ |Configuration | Memory Controller |
+ | | 1 2 3 4 |
+ |--------------+--------------+--------------+-----------------------------+
+ | Two memory | Not Intlv'ed | Not Intlv'ed | |
+ | complexes +--------------+--------------+ |
+ | | 2-way Intlv'ed | |
+ |--------------+--------------+--------------+--------------+ |
+ | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | |
+ | Three memory +--------------+--------------+--------------+ |
+ | complexes | 2-way Intlv'ed | Not Intlv'ed | |
+ | +-----------------------------+--------------+ |
+ | | 3-way Intlv'ed | |
+ +--------------+--------------+--------------+--------------+--------------+
+ | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
+ | Four memory +--------------+--------------+--------------+--------------+
+ | complexes | 2-way Intlv'ed | 2-way Intlv'ed |
+ | +-----------------------------+-----------------------------+
+ | | 4-way Intlv'ed |
+ +--------------+-----------------------------------------------------------+
+
+
+Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
======================================================
+-------------+---------------------------------------------------------+
| | Rank Interleaving |
@@ -56,6 +79,15 @@ The ways to configure the ddr interleaving mode
# superbank
setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
+ # 1KB 3-way interleaving
+ setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
+
+ # 4KB 3-way interleaving
+ setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
+
+ # 8KB 3-way interleaving
+ setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
+
# disable bank (chip-select) interleaving
setenv hwconfig "fsl_ddr:bank_intlv=null"
diff --git a/doc/README.pblimage b/doc/README.pblimage
new file mode 100644
index 00000000000..2b9bb5c5f5b
--- /dev/null
+++ b/doc/README.pblimage
@@ -0,0 +1,114 @@
+------------------------------------------------------------------
+Freescale PBL(pre-boot loader) Boot Image generation using mkimage
+------------------------------------------------------------------
+
+The CoreNet SoC's can boot directly from eSPI FLASH, SD/MMC and
+NAND, etc. These SoCs use PBL to load RCW and/or pre-initialization
+instructions. For more details refer section 5 Pre-boot loader
+specifications of reference manual P3041RM/P4080RM/P5020RM at link:
+http://www.freescale.com/webapp/search/Serp.jsp?Reference+Manuals
+
+Building PBL Boot Image and boot steps
+--------------------------------------
+
+1. Building PBL Boot Image.
+ The default Image is u-boot.pbl.
+
+ For eSPI boot(available on P3041/P4080/P5020):
+ To build the eSPI boot image:
+ make <board_name>_SPIFLASH_config
+ make u-boot.pbl
+
+ For SD boot(available on P3041/P4080/P5020):
+ To build the SD boot image:
+ make <board_name>_SDCARD_config
+ make u-boot.pbl
+
+ For Nand boot(available on P3041/P5020):
+ To build the NAND boot image:
+ make <board_name>_NAND_config
+ make u-boot.pbl
+
+
+2. pblimage support available with mkimage utility will generate Freescale PBL
+boot image that can be flashed on the board eSPI flash, SD/MMC and NAND.
+Following steps describe it in detail.
+
+ 1). Boot from eSPI flash
+ Write u-boot.pbl to eSPI flash from offset 0x0.
+ for ex in u-boot:
+ =>tftp 100000 u-boot.pbl
+ =>sf probe 0
+ =>sf erase 0 100000
+ =>sf write 100000 0 $filesize
+ Change SW1[1:5] = off off on off on.
+
+ 2). Boot from SD/MMC
+ Write u-boot.pbl to SD/MMC from offset 0x1000.
+ for ex in u-boot:
+ =>tftp 100000 u-boot.pbl
+ =>mmcinfo
+ =>mmc write 100000 8 441
+ Change SW1[1:5] = off off on on off.
+
+ 3). Boot from Nand
+ Write u-boot.pbl to Nand from offset 0x0.
+ for ex in u-boot:
+ =>tftp 100000 u-boot.pbl
+ =>nand info
+ =>nand erase 0 100000
+ =>nand write 100000 0 $filesize
+ Change SW1[1:5] = off on off off on
+ Change SW7[1:4] = on off off on
+
+Board specific configuration file specifications:
+------------------------------------------------
+1. Configuration files rcw.cfg and pbi.cfg must present in the
+board/freescale/corenet_ds/, rcw.cfg is for RCW, pbi.cfg is for
+PBI instructions. File name must not be changed since they are used
+in Makefile.
+2. These files can have empty lines and lines starting with "#" as first
+character to put comments
+
+Typical example of rcw.cfg file:
+-----------------------------------
+
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#64 bytes RCW data
+4c580000 00000000 18185218 0000cccc
+40464000 3c3c2000 58000000 61000000
+00000000 00000000 00000000 008b6000
+00000000 00000000 00000000 00000000
+
+Typical example of pbi.cfg file:
+-----------------------------------
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+09010100 00000000
+09010104 fff0000b
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff00000
+09000d08 81000013
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Initialize eSPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
+
+------------------------------------------------
+Author: Shaohui Xie<Shaohui.Xie@freescale.com>
diff --git a/doc/README.srio-boot-corenet b/doc/README.srio-boot-corenet
deleted file mode 100644
index 56b094c9a27..00000000000
--- a/doc/README.srio-boot-corenet
+++ /dev/null
@@ -1,103 +0,0 @@
-------------------------------
-SRIO Boot on Corenet Platforms
-------------------------------
-
-For some PowerPC processors with SRIO interface, boot location can be configured
-to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot
-image, ucode and ENV. All the images can be fetched from another processor's
-memory space by SRIO link connected between them.
-
-This document describes the processes based on an example implemented on P4080DS
-platforms and a RCW example with boot from SRIO configuration.
-
-Environment of the SRIO boot:
- a) Master and slave can be SOCs in one board or SOCs in separate boards.
- b) They are connected with SRIO links, whether 1x or 4x, and directly or
- through switch system.
- c) Only Master has NorFlash for booting, and all the Master's and Slave's
- U-Boot images, UCodes will be stored in this flash.
- d) Slave has its own EEPROM for RCW and PBI.
- e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot
- location to SRIO, and holdoff all the cores if needed.
-
- ---------- ----------- -----------
- | | | | | |
- | | | | | |
- | NorFlash|<----->| Master | SRIO | Slave |<---->[EEPROM]
- | | | |<===========>| |
- | | | | | |
- ---------- ----------- -----------
-
-The example based on P4080DS platform:
- Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO
- ports 0 will be connected directly and will be used for the boot from SRIO.
-
- 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff.
- 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
- 00000010: 1818 1818 0000 8888 7440 4000 0000 2000
- 00000020: f400 0000 0100 0000 0000 0000 0000 0000
- 00000030: 0000 0000 0083 0000 0000 0000 0000 0000
- 00000040: 0000 0000 0000 0000 0813 8040 698b 93fe
-
- 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff.
- 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
- 00000010: 1818 1818 0000 8888 7440 4000 0000 2000
- 00000020: f440 0000 0100 0000 0000 0000 0000 0000
- 00000030: 0000 0000 0083 0000 0000 0000 0000 0000
- 00000040: 0000 0000 0000 0000 0813 8040 063c 778f
-
- 3. Sequence in Step by Step.
- a) Update RCW for slave with boot from SRIO port 0 configuration.
- b) Program slave's U-Boot image, UCode, and ENV parameters into master's
- NorFlash.
- c) Start up master and it will boot up normally from its NorFlash.
- Then, it will finish necessary configurations for slave's boot from
- SRIO port 0.
- d) Master will set inbound SRIO windows covered slave's U-Boot image stored
- in master's NorFlash.
- e) Master will set an inbound SRIO window covered slave's UCode stored in
- master's NorFlash.
- f) Master will set an inbound SRIO window covered slave's ENV stored in
- master's NorFlash.
- g) If need to release slave's core, master will set outbound SRIO windows
- in order to configure slave's registers for the core's releasing.
- h) If all cores of slave in holdoff, slave should be powered on before all
- the above master's steps, and wait to be released by master. If not all
- cores in holdoff, that means core 0 will start up normally, slave should
- be powered on after all the above master's steps. In the startup phase
- of the slave from SRIO, it will finish some necessary configurations.
- i) Slave will set a specific TLB entry for the boot process.
- j) Slave will set a LAW entry with the TargetID SRIO port 0 for the boot.
- k) Slave will set a specific TLB entry in order to fetch UCode and ENV
- from master.
- l) Slave will set a LAW entry with the TargetID SRIO port 0 for UCode and ENV.
-
-How to use this feature:
- To use this feature, you need to focus three points.
-
- 1. Slave's RCW with SRIO boot configurations, and all cores in holdoff
- configurations if needed.
- Please refer to the examples given above.
-
- 2. U-Boot image's compilation.
- For master, U-Boot image should be generated specifically by
-
- make xxxx_SRIOBOOT_MASTER_config.
-
- For example, master U-Boot image used on P4080DS should be compiled with
-
- make P4080DS_SRIOBOOT_MASTER_config.
-
- For slave, U-Boot image should be generated specifically by
-
- make xxxx_SRIOBOOT_SLAVE_config.
-
- For example, slave U-Boot image used on P4080DS should be compiled with
-
- make P4080DS_SRIOBOOT_SLAVE_config.
-
- 3. Necessary modifications based on a specific environment.
- For a specific environment, the SRIO port for boot, the addresses of the
- slave's U-Boot image, UCode, ENV stored in master's NorFlash, and any other
- configurations can be modified in the file:
- include/configs/corenet_ds.h.
diff --git a/doc/README.srio-pcie-boot-corenet b/doc/README.srio-pcie-boot-corenet
new file mode 100644
index 00000000000..cd7e7ee9b34
--- /dev/null
+++ b/doc/README.srio-pcie-boot-corenet
@@ -0,0 +1,112 @@
+---------------------------------------
+SRIO and PCIE Boot on Corenet Platforms
+---------------------------------------
+
+For some PowerPC processors with SRIO or PCIE interface, boot location can be
+configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
+do without flash for u-boot image, ucode and ENV. All the images can be fetched
+from another processor's memory space by SRIO or PCIE link connected between
+them.
+
+This document describes the processes based on an example implemented on P4080DS
+platforms and a RCW example with boot from SRIO or PCIE configuration.
+
+Environment of the SRIO or PCIE boot:
+ a) Master and slave can be SOCs in one board or SOCs in separate boards.
+ b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
+ directly or through switch system.
+ c) Only Master has NorFlash for booting, and all the Master's and Slave's
+ U-Boot images, UCodes will be stored in this flash.
+ d) Slave has its own EEPROM for RCW and PBI.
+ e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
+ the boot location to SRIO or PCIE, and holdoff all the cores.
+
+ ---------- ----------- -----------
+ | | | | | |
+ | | | | | |
+ | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
+ | | | |<===========>| |
+ | | | | | |
+ ---------- ----------- -----------
+
+The example based on P4080DS platform:
+ Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
+ Their SRIO or PCIE ports 1 will be connected directly and will be used for
+ the boot from SRIO or PCIE.
+
+ 1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
+ 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
+ 00000010: 1818 1818 0000 8888 7440 4000 0000 2000
+ 00000020: f440 0000 0100 0000 0000 0000 0000 0000
+ 00000030: 0000 0000 0083 0000 0000 0000 0000 0000
+ 00000040: 0000 0000 0000 0000 0813 8040 063c 778f
+
+ 2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
+ 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
+ 00000010: 1818 1818 0000 8888 1440 4000 0000 2000
+ 00000020: f040 0000 0100 0000 0020 0000 0000 0000
+ 00000030: 0000 0000 0083 0000 0000 0000 0000 0000
+ 00000040: 0000 0000 0000 0000 0813 8040 547e ffc9
+
+ 3. Sequence in Step by Step.
+ a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
+ b) Program slave's U-Boot image, UCode, and ENV parameters into master's
+ NorFlash.
+ c) Set environment variable "bootmaster" to "SRIO1" or "PCIE1" and save
+ environment for master.
+ setenv bootmaster SRIO1
+ or
+ setenv bootmaster PCIE1
+ saveenv
+ d) Restart up master and it will boot up normally from its NorFlash.
+ Then, it will finish necessary configurations for slave's boot from
+ SRIO or PCIE port 1.
+ e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot
+ image stored in master's NorFlash.
+ f) Master will set an inbound SRIO or PCIE window covered slave's UCode
+ and ENV stored in master's NorFlash.
+ g) Master will set outbound SRIO or PCIE windows in order to configure
+ slave's registers for the core's releasing.
+ h) Since all cores of slave in holdoff, slave should be powered on before
+ all the above master's steps, and wait to be released by master. In the
+ startup phase of the slave from SRIO or PCIE, it will finish some
+ necessary configurations.
+ i) Slave will set a specific TLB entry for the boot process.
+ j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
+ the boot.
+ k) Slave will set a specific TLB entry in order to fetch UCode and ENV
+ from master.
+ l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
+ UCode and ENV.
+
+How to use this feature:
+ To use this feature, you need to focus those points.
+
+ 1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
+ configurations.
+ Please refer to the examples given above.
+
+ 2. U-Boot image's compilation.
+ For master, U-Boot image should be generated normally.
+
+ For example, master U-Boot image used on P4080DS should be compiled with
+
+ make P4080DS_config.
+
+ For slave, U-Boot image should be generated specifically by
+
+ make xxxx_SRIO_PCIE_BOOT_config.
+
+ For example, slave U-Boot image used on P4080DS should be compiled with
+
+ make P4080DS_SRIO_PCIE_BOOT_config.
+
+ 3. Necessary modifications based on a specific environment.
+ For a specific environment, the addresses of the slave's U-Boot image,
+ UCode, ENV stored in master's NorFlash, and any other configurations
+ can be modified in the file:
+ include/configs/corenet_ds.h.
+
+ 4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
+ or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
+ perform the role as a master for boot from SRIO or PCIE.