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authorMichael Walle <michael@walle.cc>2020-05-07 00:11:57 +0200
committerTom Rini <trini@konsulko.com>2020-05-07 11:05:00 -0400
commitfe6293a8095998affd5e46e7968485fcc332e0fa (patch)
tree9e4f87a13d4f6530ccbc3566aa6fdc1f57d0b578 /doc/device-tree-bindings
parent2b7721552a4cb4046a365a665fba3a3a848eb966 (diff)
phy: atheros: add device tree bindings and config
Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'doc/device-tree-bindings')
-rw-r--r--doc/device-tree-bindings/net/phy/atheros.txt35
1 files changed, 35 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/net/phy/atheros.txt b/doc/device-tree-bindings/net/phy/atheros.txt
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+* Qualcomm Atheros PHY Device Tree binding
+
+Required properties:
+- reg: PHY address
+
+Optional properties:
+- qca,clk-out-frequency: Clock frequency of the CLK_25M pin in Hz.
+ Either 25000000, 50000000, 62500000 or 125000000.
+- qca,clk-out-strength: Clock output buffer driver strength.
+ Supported values are defined in dt-bindings/net/qca-ar803x.h
+- qca,keep-pll-enabled: Keep the PLL running if no link is present.
+ Don't go into hibernation mode.
+ Only supported on the AR8031/AR8033.
+- vddio-supply: RGMII I/O voltage regulator
+ Only supported on the AR8031/AR8033.
+
+Optional subnodes:
+- vddio-regulator: Initial data for the VDDIO regulator, as covered
+ doc/device-tree-bindings/regulator/regulator.txt
+
+Example:
+ #include <dt-bindings/net/qca-ar803x.h>
+
+ ethernet-phy@0 {
+ reg = <0>;
+ qca-clk-out-frequency = <125000000>;
+ qca,keep-pll-enabled;
+
+ vddio-supply = <&vddio>;
+
+ vddio: vddio-regulator {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };