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authorKever Yang <kever.yang@rock-chips.com>2017-02-22 16:56:35 +0800
committerSimon Glass <sjg@chromium.org>2017-03-16 16:03:45 -0600
commitfa437430ad9861886f5766151757a99de647d086 (patch)
tree670ca3034201d5194678efbf1e6826266ad6d3ea /doc/device-tree-bindings
parent26d5ee8f9b29e06272f8bab052b12df90fe7b6f8 (diff)
rockchip: arm64: rk3399: add ddr controller driver
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from coreboot, support 4GB lpddr3 in this version. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Added rockchip: tag: Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'doc/device-tree-bindings')
-rw-r--r--doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt42
1 files changed, 42 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt b/doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt
new file mode 100644
index 00000000000..a15dc5d1f85
--- /dev/null
+++ b/doc/device-tree-bindings/clock/rockchip,rk3399-dmc.txt
@@ -0,0 +1,42 @@
+Rockchip Dynamic Memory Controller Driver
+Required properties:
+- compatible: "rockchip,rk3399-dmc", "syscon"
+- rockchip,cru: this driver should access cru regs, so need get cru here
+- rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here
+- rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here
+- rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here
+- rockchip,cic: this driver should access cic regs, so need get cic here
+- reg: dynamic ram protocol controller(PCTL) address, PHY Independent(PI) address, phy controller(PHYCTL) address and memory schedule(MSCH) address
+- clock: must include clock specifiers corresponding to entries in the clock-names property.
+ Must contain
+ dmc_clk: for ddr working frequency
+- rockchip,sdram-params: SDRAM parameters, including all the information by ddr driver:
+ Must contain
+ Genarate by vendor tool and adjust for U-Boot dtsi.
+
+Example:
+ dmc: dmc {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3399-dmc";
+ devfreq-events = <&dfi>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_DDRCLK>;
+ clock-names = "dmc_clk";
+ reg = <0x0 0xffa80000 0x0 0x0800
+ 0x0 0xffa80800 0x0 0x1800
+ 0x0 0xffa82000 0x0 0x2000
+ 0x0 0xffa84000 0x0 0x1000
+ 0x0 0xffa88000 0x0 0x0800
+ 0x0 0xffa88800 0x0 0x1800
+ 0x0 0xffa8a000 0x0 0x2000
+ 0x0 0xffa8c000 0x0 0x1000>;
+ };
+
+ &dmc {
+ rockchip,sdram-params = <
+ 0x2
+ 0xa
+ 0x3
+ ...
+ >;
+ };