diff options
| author | Vignesh R <vigneshr@ti.com> | 2019-02-05 11:29:28 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2019-02-07 15:33:22 +0530 |
| commit | 6d82517836418f984b7b4c05cf1427d7b49b1169 (patch) | |
| tree | 847f72132490b66b2a8c6060f45fa8d228090ff4 /doc/SPI/README.ti_qspi_dra_test | |
| parent | 75b2ec2a22964c7e8c51b2e4c903284fe6013b4f (diff) | |
configs: Don't use SPI_FLASH_BAR as default
Now that new SPI NOR layer uses stateless 4 byte opcodes by default,
don't enable SPI_FLASH_BAR. For SPI controllers that cannot support
4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c,
renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to
not break functionality.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
Diffstat (limited to 'doc/SPI/README.ti_qspi_dra_test')
| -rw-r--r-- | doc/SPI/README.ti_qspi_dra_test | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/doc/SPI/README.ti_qspi_dra_test b/doc/SPI/README.ti_qspi_dra_test index fe37857236..e89f53587f 100644 --- a/doc/SPI/README.ti_qspi_dra_test +++ b/doc/SPI/README.ti_qspi_dra_test @@ -22,7 +22,6 @@ Commands to erase/write u-boot/mlo to flash device -------------------------------------------------- U-Boot# sf probe 0 SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB, mapped at 5c000000 -SF: Warning - Only lower 16MiB accessible, Full access #define CONFIG_SPI_FLASH_BAR U-Boot# sf erase 0 0x10000 SF: 65536 bytes @ 0x0 Erased: OK U-Boot# sf erase 0x20000 0x10000 |