diff options
author | Rick Chen <rick@andestech.com> | 2017-12-26 13:55:59 +0800 |
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committer | Tom Rini <trini@konsulko.com> | 2018-01-12 08:05:12 -0500 |
commit | 3fafced74df234c708e645a373a70db665e4e6ce (patch) | |
tree | 996484df8a7399bb4ac2585937cb04092d280bb4 /doc/README.NX25 | |
parent | 068feb9b86d991283c43b56e36094f4e6f484d04 (diff) |
riscv: doc: Add relative doc to describe RISC-V
Add documents to describe NX25 and AE250.
Also update other documents for RISC-V.
Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Diffstat (limited to 'doc/README.NX25')
-rw-r--r-- | doc/README.NX25 | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/doc/README.NX25 b/doc/README.NX25 new file mode 100644 index 0000000000..9f054e5cf2 --- /dev/null +++ b/doc/README.NX25 @@ -0,0 +1,46 @@ +NX25 is Andes CPU IP to adopt RISC-V architecture. + +Features +======== + +CPU Core + - 5-stage in-order execution pipeline + - Hardware Multiplier + - radix-2/radix-4/radix-16/radix-256/fast + - Hardware Divider + - Optional branch prediction + - Machine mode and optional user mode + - Optional performance monitoring + +ISA + - RV64I base integer instructions + - RVC for 16-bit compressed instructions + - RVM for multiplication and division instructions + +Memory subsystem + - I & D local memory + - Size: 4KB to 16MB + - Memory subsyetem soft-error protection + - Protection scheme: parity-checking or error-checking-and-correction (ECC) + - Automatic hardware error correction + +Bus + - Interface Protocol + - Synchronous AHB (32-bit/64-bit data-width), or + - Synchronous AXI4 (64-bit data-width) + +Power management + - Wait for interrupt (WFI) mode + +Debug + - Configurable number of breakpoints: 2/4/8 + - External Debug Module + - AHB slave port + - External JTAG debug transport module + +Platform Level Interrupt Controller (PLIC) + - AHB slave port + - Configurable number of interrupts: 1-1023 + - Configurable number of interrupt priorities: 3/7/15/63/127/255 + - Configurable number of targets: 1-16 + - Preempted interrupt priority stack |