diff options
| author | Srikanth Srinivasan <srikanth.srinivasan@freescale.com> | 2010-03-30 14:03:30 -0500 |
|---|---|---|
| committer | Scott Sweeny <scott.sweeny@timesys.com> | 2010-09-29 17:32:30 -0400 |
| commit | 04cbb96db06c5a1fba1a80d00f322b25ab656ede (patch) | |
| tree | cb7d8c66909e156c550e62e0d75ba2253c970e6a /cpu | |
| parent | 7ce9279b6b3d9edf67e44f4de1d04bf26ed409e1 (diff) | |
P1022DS: Enable ddr_sdram_cfg[hse] for the platform
This patch enables DDR_SDRAM_CFG[HSE] for P1022DS.
This is needed mainly for higher frequencies but can
be left on for < 800MHz DDR frequency.
Disabled DDR_SDRAM_CFG[2T_EN] for 800MHz operation.
Also added debug prints for additional ddr registers.
Tested with the Hynix HMT125U7BFR8C-H9 and ELPIDA EBJ21EE8BAFA-DJ-E,
passed at 667MT/s or 800MT/s.
Tested-by: Jiang Yutang <B14898@freescale.com>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc8xxx/ddr/ctrl_regs.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 2505041450..0bfc3bff6d 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -906,6 +906,7 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, clk_adjust = popts->clk_adjust; ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23; + debug("FSLDDR: sdram_clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); } /* DDR Initialization Address (DDR_INIT_ADDR) */ @@ -998,6 +999,7 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) | ((zqoper & 0xF) << 16) | ((zqcs & 0xF) << 8) ); + debug("FSLDDR: ddr_zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); } /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ @@ -1057,6 +1059,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, | ((wrlvl_wlr & 0x7) << 8) | ((wrlvl_start & 0x1F) << 0) ); + debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); } /* DDR Self Refresh Counter (DDR_SR_CNTR) */ |