ColdFire: Added MCF5275 cpu support.

Signed-off-by: Matthew Fettke <mfettke@videon-central.com>
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Acked-by: John Rigby <jrigby@freescale.com>

6 files changed, 224 insertions, 3 deletions

diff --git a/cpu/mcf52x2/config.mk b/cpu/mcf52x2/config.mk
index c3899c507ec..650e340aee8 100644
--- a/cpu/mcf52x2/config.mk
+++ b/cpu/mcf52x2/config.mk
@@ -30,6 +30,7 @@ is5249:=$(shell grep CONFIG_M5249 $(TOPDIR)/include/$(cfg))
 is5253:=$(shell grep CONFIG_M5253 $(TOPDIR)/include/$(cfg))
 is5271:=$(shell grep CONFIG_M5271 $(TOPDIR)/include/$(cfg))
 is5272:=$(shell grep CONFIG_M5272 $(TOPDIR)/include/$(cfg))
+is5275:=$(shell grep CONFIG_M5275 $(TOPDIR)/include/$(cfg))
 is5282:=$(shell grep CONFIG_M5282 $(TOPDIR)/include/$(cfg))
 
 
@@ -47,6 +48,9 @@ endif
 ifneq (,$(findstring CONFIG_M5272,$(is5272)))
 PLATFORM_CPPFLAGS += -mcpu=5272
 endif
+ifneq (,$(findstring CONFIG_M5275,$(is5275)))
+PLATFORM_CPPFLAGS += -mcpu=5275
+endif
 ifneq (,$(findstring CONFIG_M5282,$(is5282)))
 PLATFORM_CPPFLAGS += -mcpu=5282
 endif
diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c
index 71ea408aa5e..d5d3d339c51 100644
--- a/cpu/mcf52x2/cpu.c
+++ b/cpu/mcf52x2/cpu.c
@@ -6,6 +6,9 @@
  * (C) Copyright 2005
  * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
  *
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -180,6 +183,69 @@ int watchdog_init(void)
 
 #endif				/* #ifdef CONFIG_M5272 */
 
+#ifdef	CONFIG_M5275
+int do_reset(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+	volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+
+	udelay(1000);
+
+	rcm->rcr = RCM_RCR_SOFTRST;
+
+	/* we don't return! */
+	return 0;
+};
+
+int checkcpu(void)
+{
+	char buf[32];
+
+	printf("CPU:   Freescale Coldfire MCF5275 at %s MHz\n",
+			strmhz(buf, CFG_CLK));
+	return 0;
+};
+
+
+#if defined(CONFIG_WATCHDOG)
+/* Called by macro WATCHDOG_RESET */
+void watchdog_reset(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+	wdt->wsr = 0x5555;
+	wdt->wsr = 0xAAAA;
+}
+
+int watchdog_disable(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+	wdt->wsr = 0x5555; /* reset watchdog counter */
+	wdt->wsr = 0xAAAA;
+	wdt->wcr = 0;	/* disable watchdog timer */
+
+	puts("WATCHDOG:disabled\n");
+	return (0);
+}
+
+int watchdog_init(void)
+{
+	volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+
+	wdt->wcr = 0;	/* disable watchdog */
+
+	/* set timeout and enable watchdog */
+	wdt->wmr =
+		((CONFIG_WATCHDOG_TIMEOUT * CFG_HZ) / (32768 * 1000)) - 1;
+	wdt->wsr = 0x5555; /* reset watchdog counter */
+	wdt->wsr = 0xAAAA;
+
+	puts("WATCHDOG:enabled\n");
+	return (0);
+}
+#endif				/* #ifdef CONFIG_WATCHDOG */
+
+#endif				/* #ifdef CONFIG_M5275 */
+
 #ifdef	CONFIG_M5282
 int checkcpu(void)
 {
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 458b85ef144..207a37e7d57 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -10,6 +10,9 @@
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  * Hayden Fraser (Hayden.Fraser@freescale.com)
  *
+ * MCF5275 additions
+ * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -245,6 +248,114 @@ void uart_port_conf(void)
 }
 #endif				/* #if defined(CONFIG_M5272) */
 
+#if defined(CONFIG_M5275)
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	/* if we come from RAM we assume the CPU is
+	 * already initialized.
+	 */
+
+#ifndef CONFIG_MONITOR_IS_IN_RAM
+	volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
+	volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
+	volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
+
+	/* Kill watchdog so we can initialize the PLL */
+	wdog_reg->wcr = 0;
+
+	/* Memory Controller: */
+	/* Flash */
+	csctrl_reg->ar0 = CFG_AR0_PRELIM;
+	csctrl_reg->cr0 = CFG_CR0_PRELIM;
+	csctrl_reg->mr0 = CFG_MR0_PRELIM;
+
+#if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
+	csctrl_reg->ar1 = CFG_AR1_PRELIM;
+	csctrl_reg->cr1 = CFG_CR1_PRELIM;
+	csctrl_reg->mr1 = CFG_MR1_PRELIM;
+#endif
+
+#if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
+	csctrl_reg->ar2 = CFG_AR2_PRELIM;
+	csctrl_reg->cr2 = CFG_CR2_PRELIM;
+	csctrl_reg->mr2 = CFG_MR2_PRELIM;
+#endif
+
+#if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
+	csctrl_reg->ar3 = CFG_AR3_PRELIM;
+	csctrl_reg->cr3 = CFG_CR3_PRELIM;
+	csctrl_reg->mr3 = CFG_MR3_PRELIM;
+#endif
+
+#if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
+	csctrl_reg->ar4 = CFG_AR4_PRELIM;
+	csctrl_reg->cr4 = CFG_CR4_PRELIM;
+	csctrl_reg->mr4 = CFG_MR4_PRELIM;
+#endif
+
+#if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
+	csctrl_reg->ar5 = CFG_AR5_PRELIM;
+	csctrl_reg->cr5 = CFG_CR5_PRELIM;
+	csctrl_reg->mr5 = CFG_MR5_PRELIM;
+#endif
+
+#if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
+	csctrl_reg->ar6 = CFG_AR6_PRELIM;
+	csctrl_reg->cr6 = CFG_CR6_PRELIM;
+	csctrl_reg->mr6 = CFG_MR6_PRELIM;
+#endif
+
+#if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
+	csctrl_reg->ar7 = CFG_AR7_PRELIM;
+	csctrl_reg->cr7 = CFG_CR7_PRELIM;
+	csctrl_reg->mr7 = CFG_MR7_PRELIM;
+#endif
+
+#endif				/* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+
+#ifdef CONFIG_FSL_I2C
+	gpio_reg->par_feci2c = 0x000F;
+#endif
+
+	/* enable instruction cache now */
+	icache_enable();
+}
+
+/*
+ * initialize higher level parts of CPU like timers
+ */
+int cpu_init_r(void)
+{
+	return (0);
+}
+
+void uart_port_conf(void)
+{
+	volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
+
+	/* Setup Ports: */
+	switch (CFG_UART_PORT) {
+	case 0:
+		gpio->par_uart |= UART0_ENABLE_MASK;
+		break;
+	case 1:
+		gpio->par_uart |= UART1_ENABLE_MASK;
+		break;
+	case 2:
+		gpio->par_uart |= UART2_ENABLE_MASK;
+		break;
+	}
+}
+#endif				/* #if defined(CONFIG_M5275) */
+
 #if defined(CONFIG_M5282)
 /*
  * Breath some life into the CPU...
diff --git a/cpu/mcf52x2/interrupts.c b/cpu/mcf52x2/interrupts.c
index 9167cec6988..b8fb7bb0eec 100644
--- a/cpu/mcf52x2/interrupts.c
+++ b/cpu/mcf52x2/interrupts.c
@@ -59,7 +59,7 @@ void dtimer_intr_setup(void)
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
 
-#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
+#if defined(CONFIG_M5282) || defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
 	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
@@ -81,7 +81,7 @@ void dtimer_intr_setup(void)
 	intp->imrl0 &= ~CFG_TMRINTR_MASK;
 }
 #endif				/* CONFIG_MCFTMR */
-#endif				/* CONFIG_M5282 | CONFIG_M5271 */
+#endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
 
 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
 int interrupt_init(void)
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index bc1e20023b1..85a5c4de38f 100644
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -64,8 +64,18 @@ int get_clocks (void)
 
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
 
+#if defined(CONFIG_M5275)
+	volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
+
+        /* Setup PLL */
+        pll->syncr = 0x01080000;
+        while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+        pll->syncr = 0x01000000;
+        while (!(pll->synsr & FMPLL_SYNSR_LOCK));
+#endif
+
 	gd->cpu_clk = CFG_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
 	gd->bus_clk = gd->cpu_clk / 2;
 #else
 	gd->bus_clk = gd->cpu_clk;
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index c086ca7bebf..f6c58c2fef1 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -197,6 +197,17 @@ _copy_flash:
 _after_flash_copy:
 #endif
 
+#ifdef CONFIG_M5275
+	/* Initialize IPSBAR */
+	move.l	#(CFG_MBAR + 1), %d0		/* set IPSBAR address + valid flag */
+	move.l	%d0, 0x40000000
+/*	movec	%d0, %MBAR */
+
+	/* Initialize RAMBAR: locate SRAM and validate it */
+	move.l	#(CFG_INIT_RAM_ADDR + 0x21), %d0
+	movec	%d0, %RAMBAR1
+#endif
+
 #if 0
 	/* invalidate and disable cache */
 	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
@@ -394,6 +405,25 @@ icache_enable:
 	rts
 #endif
 
+#if  defined(CONFIG_M5275)
+/*
+ * Instruction cache only
+ */
+	.globl	icache_enable
+icache_enable:
+	move.l	#0x01400000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#0x0000c000, %d0		/* Setup SDRAM caching */
+	movec	%d0, %ACR0			/* Enable cache */
+	move.l	#0x00000000, %d0		/* No other caching */
+	movec	%d0, %ACR1			/* Enable cache */
+	move.l	#0x80400100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	moveq	#1, %d0
+	move.l	%d0, icache_state
+	rts
+#endif
+
 #ifdef CONFIG_M5282
 	.globl	icache_enable
 icache_enable: