diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2008-12-06 18:06:58 -0500 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2009-03-23 15:14:54 -0400 |
| commit | 3986e981f565c08f10c7e526af8cb518d741c349 (patch) | |
| tree | 12b89f7b7d1adba7b149f5bb97bb7ca33960e2b1 /cpu | |
| parent | 7e1d212b6da492c6ea32c62af92e185284f41291 (diff) | |
Blackfin: handle reboot anomaly 432
Workaround anomaly 432:
The bfrom_SysControl() firmware function does not clear the SIC_IWR1
register before executing the PLL programming sequence. Therefore, any
interrupt enabled in the SIC_IWR1 register prior to the call to
bfrom_SysControl() can prematurely terminate the idle sequence required
for the PLL to relock properly. SIC_IWR0 is properly handled.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/blackfin/initcode.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index 342b96ab8f1..1b58f997dd4 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -273,8 +273,14 @@ void initcode(ADI_BOOT_DATA *bootstruct) memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL; memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL; memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL; +#if ANOMALY_05000432 + bfin_write_SIC_IWR1(0); +#endif syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT | (CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL); +#if ANOMALY_05000432 + bfin_write_SIC_IWR1(-1); +#endif } else { serial_putc('L'); |