* Cleanup lowboot code for MPC5200

* Minor code cleanup (coding style)

* Patch by Reinhard Meyer, 30 Dec 2003:
  - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
  - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
  - turned debug print of PHY registers into a function (called in two places)
  - added support for EMK MPC5200 based modules

* Fix MPC8xx PLPRCR_MFD_SHIFT typo

* Add support for TQM866M modules

* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)

* Fix a few compiler warnings

7 files changed, 165 insertions, 170 deletions

diff --git a/cpu/coldfire/Makefile b/cpu/coldfire/Makefile
index 085d840c0f8..3976f5689d9 100644
--- a/cpu/coldfire/Makefile
+++ b/cpu/coldfire/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(CPU).a
 
-START	= 
+START	=
 OBJS	= kgdb.o serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o
 
 all:	.depend $(START) $(LIB)
diff --git a/cpu/coldfire/fec.c b/cpu/coldfire/fec.c
index 53a93c1ceb4..50627415ecf 100644
--- a/cpu/coldfire/fec.c
+++ b/cpu/coldfire/fec.c
@@ -27,7 +27,6 @@
 #include <command.h>
 
 
-
 /**************************************************************
  *
  * FEC Ethernet Initialization Routine
@@ -50,18 +49,14 @@
 #define	FEC_RESET_DELAY		50000
 
 
-
 /* Ethernet Transmit and Receive Buffers */
 #define DBUF_LENGTH  1520
-
 #define TX_BUF_CNT 2
-
 #define TOUT_LOOP 100
 
-#define PKT_MAXBUF_SIZE         1518
-#define PKT_MINBUF_SIZE         64
-#define PKT_MAXBLR_SIZE         1520
-
+#define PKT_MAXBUF_SIZE		1518
+#define PKT_MINBUF_SIZE		64
+#define PKT_MAXBLR_SIZE		1520
 
 
 #ifdef CONFIG_M5272
@@ -76,11 +71,10 @@
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
 
 
-
 static char txbuf[DBUF_LENGTH];
 
-static uint rxIdx;	/* index of the current RX buffer */
-static uint txIdx;	/* index of the current TX buffer */
+static uint rxIdx;		/* index of the current RX buffer */
+static uint txIdx;		/* index of the current TX buffer */
 
 /*
   * FEC Ethernet Tx and Rx buffer descriptors allocated at the
@@ -89,14 +83,14 @@ static uint txIdx;	/* index of the current TX buffer */
   */
 
 typedef volatile struct CommonBufferDescriptor {
-    cbd_t rxbd[PKTBUFSRX];		/* Rx BD */
-    cbd_t txbd[TX_BUF_CNT];		/* Tx BD */
+	cbd_t rxbd[PKTBUFSRX];	/* Rx BD */
+	cbd_t txbd[TX_BUF_CNT];	/* Tx BD */
 } RTXBD;
 
 static RTXBD *rtx = 0x380000;
 
 
-int eth_send(volatile void *packet, int length)
+int eth_send (volatile void *packet, int length)
 {
 	int j, rc;
 	volatile fec_t *fecp = FEC_ADDR;
@@ -105,35 +99,37 @@ int eth_send(volatile void *packet, int length)
 	 * Wait for ready
 	 */
 	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
-		udelay(1);
+	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
+	       && (j < TOUT_LOOP)) {
+		udelay (1);
 		j++;
 	}
-	if (j>=TOUT_LOOP) {
-		printf("TX not ready\n");
+	if (j >= TOUT_LOOP) {
+		printf ("TX not ready\n");
 	}
 
-	rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
-	rtx->txbd[txIdx].cbd_datlen  = length;
+	rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
+	rtx->txbd[txIdx].cbd_datlen = length;
 	rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
 
 	/* Activate transmit Buffer Descriptor polling */
-	fecp->fec_x_des_active = 0x01000000;	/* Descriptor polling active	*/
+	fecp->fec_x_des_active = 0x01000000;	/* Descriptor polling active    */
 
 	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
-		udelay(1);
+	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
+	       && (j < TOUT_LOOP)) {
+		udelay (1);
 		j++;
 	}
-	if (j>=TOUT_LOOP) {
-		printf("TX timeout\n");
+	if (j >= TOUT_LOOP) {
+		printf ("TX timeout\n");
 	}
 #ifdef ET_DEBUG
-	printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
-	__FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
-	(rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
+	printf ("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
+		__FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
+		(rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
 #endif
-	/* return only status bits */;
+	/* return only status bits */ ;
 	rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
 
 	txIdx = (txIdx + 1) % TX_BUF_CNT;
@@ -141,48 +137,49 @@ int eth_send(volatile void *packet, int length)
 	return rc;
 }
 
-int eth_rx(void)
+int eth_rx (void)
 {
 	int length;
 	volatile fec_t *fecp = FEC_ADDR;
 
-   for (;;)
-   {     
-	/* section 16.9.23.2 */
-	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-		length = -1;
-		break;     /* nothing received - leave for() loop */
-	}
+	for (;;) {
+		/* section 16.9.23.2 */
+		if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+			length = -1;
+			break;	/* nothing received - leave for() loop */
+		}
 
-	length = rtx->rxbd[rxIdx].cbd_datlen;
+		length = rtx->rxbd[rxIdx].cbd_datlen;
 
-	if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
+		if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
 #ifdef ET_DEBUG
-		printf("%s[%d] err: %x\n",
-		__FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc);
+			printf ("%s[%d] err: %x\n",
+				__FUNCTION__, __LINE__,
+				rtx->rxbd[rxIdx].cbd_sc);
 #endif
-	} else {
-		/* Pass the packet up to the protocol layers. */
-		NetReceive(NetRxPackets[rxIdx], length - 4);
+		} else {
+			/* Pass the packet up to the protocol layers. */
+			NetReceive (NetRxPackets[rxIdx], length - 4);
+		}
+
+		/* Give the buffer back to the FEC. */
+		rtx->rxbd[rxIdx].cbd_datlen = 0;
+
+		/* wrap around buffer index when necessary */
+		if ((rxIdx + 1) >= PKTBUFSRX) {
+			rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
+				(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
+			rxIdx = 0;
+		} else {
+			rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+			rxIdx++;
+		}
+
+		/* Try to fill Buffer Descriptors */
+		fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
 	}
 
-	/* Give the buffer back to the FEC. */
-	rtx->rxbd[rxIdx].cbd_datlen = 0;
-
-	/* wrap around buffer index when necessary */
-	if ((rxIdx + 1) >= PKTBUFSRX) {
-           rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
-	   rxIdx = 0;
-	} else {
-           rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-	   rxIdx++;
-	}
-	
-	/* Try to fill Buffer Descriptors */
-	fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active	*/
-   }
-
-   return length;
+	return length;
 }
 
 
@@ -191,7 +188,7 @@ int eth_init (bd_t * bd)
 
 	int i;
 	volatile fec_t *fecp = FEC_ADDR;
-	
+
 	/* Whack a reset.
 	 * A delay is required between a reset of the FEC block and
 	 * initialization of other FEC registers because the reset takes
@@ -214,21 +211,21 @@ int eth_init (bd_t * bd)
 	/* We use strictly polling mode only
 	 */
 	fecp->fec_imask = 0;
-	
+
 	/* Clear any pending interrupt */
 	fecp->fec_ievent = 0xffffffff;
-	
-	/* Set station address	 */
+
+	/* Set station address   */
 #define ea bd->bi_enetaddr
-	fecp->fec_addr_low   =	(ea[0] << 24) | (ea[1] << 16) |
-				(ea[2] <<  8) | (ea[3]        ) ;
-	fecp->fec_addr_high  =	(ea[4] << 24) | (ea[5] << 16  ) ;
+	fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
+		(ea[2] << 8) | (ea[3]);
+	fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
 #undef ea
 
 	/* Clear multicast address hash table
 	 */
 	fecp->fec_hash_table_high = 0;
-	fecp->fec_hash_table_low  = 0;
+	fecp->fec_hash_table_low = 0;
 
 	/* Set maximum receive buffer size.
 	 */
@@ -246,8 +243,8 @@ int eth_init (bd_t * bd)
 	 *     Empty, Wrap
 	 */
 	for (i = 0; i < PKTBUFSRX; i++) {
-		rtx->rxbd[i].cbd_sc      = BD_ENET_RX_EMPTY;
-		rtx->rxbd[i].cbd_datlen  = 0;	/* Reset */
+		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
 		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
 	}
 	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
@@ -258,8 +255,8 @@ int eth_init (bd_t * bd)
 	 *    Last, Tx CRC
 	 */
 	for (i = 0; i < TX_BUF_CNT; i++) {
-	        rtx->txbd[i].cbd_sc      = BD_ENET_TX_LAST | BD_ENET_TX_TC;
-		rtx->txbd[i].cbd_datlen  = 0;	/* Reset */
+		rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
+		rtx->txbd[i].cbd_datlen = 0;	/* Reset */
 		rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
 	}
 	rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
@@ -273,8 +270,8 @@ int eth_init (bd_t * bd)
 	 */
 
 	/* Half duplex mode */
-	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE<<16) | FEC_RCNTRL_MII_MODE;
-	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE<<16) | FEC_RCNTRL_MII_MODE;
+	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16) | FEC_RCNTRL_MII_MODE;
+	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16) | FEC_RCNTRL_MII_MODE;
 	fecp->fec_x_cntrl = 0;
 
 	fecp->fec_mii_speed = 0;
@@ -284,17 +281,16 @@ int eth_init (bd_t * bd)
 	fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
 
 	/* And last, try to fill Rx Buffer Descriptors */
-	fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active	*/
+	fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
 
 	return 1;
 }
 
 
-
-void eth_halt(void)
+void eth_halt (void)
 {
 	volatile fec_t *fecp = FEC_ADDR;
+
 	fecp->fec_ecntrl = 0;
 }
-
 #endif
diff --git a/cpu/coldfire/start.S b/cpu/coldfire/start.S
index 7e02661e0a3..44542231db9 100644
--- a/cpu/coldfire/start.S
+++ b/cpu/coldfire/start.S
@@ -14,7 +14,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -26,8 +26,8 @@
 #include <config.h>
 #include "version.h"
 
-#ifndef  CONFIG_IDENT_STRING
-#define  CONFIG_IDENT_STRING ""
+#ifndef	 CONFIG_IDENT_STRING
+#define	 CONFIG_IDENT_STRING ""
 #endif
 
 #define MCF_MBAR 0x10000000
@@ -38,30 +38,30 @@
 
 	.text
 
-        .globl  _start
+	.globl	_start
 _start:
 	nop
 	nop
 	move.w #0x2700,%sr
 
-        move.l  #0, %d0
-        movec   %d0, %VBR
+	move.l	#0, %d0
+	movec	%d0, %VBR
 
 #ifdef CONFIG_M5272
-	move.l  #(MCF_MBAR+1), %d0
-        move.c  %d0, %MBAR
-
-	move.l  #(MEM_BUILTIN_ADDR+1), %d0
-        movec   %d0, %RAMBAR0
-
-	move.l  #0x01000000, %d0                /* Invalidate cache cmd */
-        movec   %d0, %CACR                      /* Invalidate cache */
-        move.l  #0x0000c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR0                      /* Enable cache */
-        move.l  #0xff00c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR1                      /* Enable cache */
-        move.l  #0x80000100, %d0                /* Setup cache mask */
-        movec   %d0, %CACR                      /* Enable cache */
+	move.l	#(MCF_MBAR+1), %d0
+	move.c	%d0, %MBAR
+
+	move.l	#(MEM_BUILTIN_ADDR+1), %d0
+	movec	%d0, %RAMBAR0
+
+	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#0x0000c000, %d0		/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+	move.l	#0xff00c000, %d0		/* Setup cache mask */
+	movec	%d0, %ACR1			/* Enable cache */
+	move.l	#0x80000100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
 #endif
 
 	move.l	#_sbss,%a0
@@ -71,8 +71,8 @@ _start:
 	cmp.l	%a0,%d0
 	bne.s	1b
 
-/*	move.l  #MEM_BUILTIN_ADDR+MEM_BUILTIN_SIZE, %sp */
-	move.l  #DRAM_ADDR+DRAM_SIZE, %sp
+/*	move.l	#MEM_BUILTIN_ADDR+MEM_BUILTIN_SIZE, %sp */
+	move.l	#DRAM_ADDR+DRAM_SIZE, %sp
 	clr.l %sp@-
 
 	jsr board_init_f
@@ -107,44 +107,44 @@ addresserror_handler:
 	lea %sp@(60),%sp
 	rte
 
-	.globl  get_endaddr
+	.globl	get_endaddr
 get_endaddr:
 	movel #_end,%d0
 	rts
 
 #ifdef CONFIG_M5272
-	.globl  icache_enable
+	.globl	icache_enable
 icache_enable:
-	move.l  #0x01000000, %d0                /* Invalidate cache cmd */
-        movec   %d0, %CACR                      /* Invalidate cache */
-        move.l  #0x0000c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR0                      /* Enable cache */
-        move.l  #0xff00c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR1                      /* Enable cache */
-        move.l  #0x80000100, %d0                /* Setup cache mask */
-        movec   %d0, %CACR                      /* Enable cache */
+	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#0x0000c000, %d0		/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+	move.l	#0xff00c000, %d0		/* Setup cache mask */
+	movec	%d0, %ACR1			/* Enable cache */
+	move.l	#0x80000100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
 	moveq	#1, %d0
 	move.l	%d0, icache_state
 	rts
 
-	.globl  icache_disable
+	.globl	icache_disable
 icache_disable:
-        move.l  #0x00000100, %d0                /* Setup cache mask */
-        movec   %d0, %CACR                      /* Enable cache */
-	clr.l   %d0				/* Setup cache mask */
-        movec   %d0, %ACR0                      /* Enable cache */
-        movec   %d0, %ACR1                      /* Enable cache */
+	move.l	#0x00000100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	clr.l	%d0				/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+	movec	%d0, %ACR1			/* Enable cache */
 	moveq	#0, %d0
 	move.l	%d0, icache_state
 	rts
 #endif
 
 #ifdef CONFIG_M5282
-	.globl  icache_enable
+	.globl	icache_enable
 icache_enable:
 	rts
 
-	.globl  icache_disable
+	.globl	icache_disable
 icache_disable:
 	rts
 #endif
@@ -158,7 +158,7 @@ icache_status:
 icache_state:
 	.long	1
 
-	.globl  version_string
+	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
 	.ascii " (", __DATE__, " - ", __TIME__, ")"
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 74b786dfb1f..e48fa88b5d2 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -36,6 +36,33 @@ typedef struct {
 } NBUF;
 
 /********************************************************************/
+#if (DEBUG & 0x2)
+static void mpc5xxx_fec_phydump (void)
+{
+	uint16 phyStatus, i;
+	uint8 phyAddr = CONFIG_PHY_ADDR;
+	uint8 reg_mask[] = {
+#if CONFIG_PHY_TYPE == 0x79c874	/* AMD Am79C874 */
+		/* regs to print: 0...7, 16...19, 21, 23, 24 */
+		1, 1, 1, 1,  1, 1, 1, 1,     0, 0, 0, 0,  0, 0, 0, 0,
+		1, 1, 1, 1,  0, 1, 0, 1,     1, 0, 0, 0,  0, 0, 0, 0,
+#else
+		/* regs to print: 0...8, 16...20 */
+		1, 1, 1, 1,  1, 1, 1, 1,     1, 0, 0, 0,  0, 0, 0, 0,
+		1, 1, 1, 1,  1, 0, 0, 0,     0, 0, 0, 0,  0, 0, 0, 0,
+#endif
+	};
+
+	for (i = 0; i < 32; i++) {
+		if (reg_mask[i]) {
+			miiphy_read(phyAddr, i, &phyStatus);
+			printf("Mii reg %d: 0x%04x\n", i, phyStatus);
+		}
+	}
+}
+#endif
+
+/********************************************************************/
 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
 {
 	int ix;
@@ -211,7 +238,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 	DECLARE_GLOBAL_DATA_PTR;
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
 	struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-	const uint8 phyAddr = 0;	/* Only one PHY */
+	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
 
 #if (DEBUG & 0x1)
 	printf ("mpc5xxx_fec_init... Begin\n");
@@ -472,21 +499,11 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
 	 */
 	fec->eth->ecntrl |= 0x00000006;
 
-	if (fec->xcv_type != SEVENWIRE) {
 #if (DEBUG & 0x2)
-		uint16 phyStatus, i;
-		uint8 phyAddr = 0;
-
-		for (i = 0; i < 9; i++) {
-			miiphy_read(phyAddr, i, &phyStatus);
-			printf("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
-		for (i = 16; i < 21; i++) {
-			miiphy_read(phyAddr, i, &phyStatus);
-			printf("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
+	if (fec->xcv_type != SEVENWIRE)
+		mpc5xxx_fec_phydump ();
 #endif
-	}
+
 	/*
 	 * Enable SmartDMA receive task
 	 */
@@ -509,22 +526,10 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
 	int counter = 0xffff;
 
 #if (DEBUG & 0x2)
-	if (fec->xcv_type != SEVENWIRE) {
-		uint16 phyStatus, i;
-		uint8 phyAddr = 0;
-
-		for (i = 0; i < 9; i++) {
-			miiphy_read(phyAddr, i, &phyStatus);
-			printf("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
-		for (i = 16; i < 21; i++) {
-			miiphy_read(phyAddr, i, &phyStatus);
-			printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
-	}
+	if (fec->xcv_type != SEVENWIRE)
+		mpc5xxx_fec_phydump ();
 #endif
 
-
 	/*
 	 * mask FEC chip interrupts
 	 */
@@ -587,7 +592,7 @@ static void mpc5xxx_fec_halt(struct eth_device *dev)
 
 static void tfifo_print(mpc5xxx_fec_priv *fec)
 {
-	uint16 phyAddr = 0;
+	uint16 phyAddr = CONFIG_PHY_ADDR;
 	uint16 phyStatus;
 
 	if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
@@ -611,7 +616,7 @@ static void tfifo_print(mpc5xxx_fec_priv *fec)
 
 static void rfifo_print(mpc5xxx_fec_priv *fec)
 {
-	uint16 phyAddr = 0;
+	uint16 phyAddr = CONFIG_PHY_ADDR;
 	uint16 phyStatus;
 
 	if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
@@ -825,12 +830,12 @@ int mpc5xxx_fec_initialize(bd_t * bis)
 	fec->eth = (ethernet_regs *)MPC5XXX_FEC;
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#ifdef CONFIG_ICECUBE
-#ifndef CONFIG_FEC_10MBIT
+#if defined(CONFIG_ICECUBE) || defined(CONFIG_TOP5200)
+#  ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
-#else
+#  else
 	fec->xcv_type = MII10;
-#endif
+#  endif
 #else
 #error fec->xcv_type not initialized.
 #endif
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index e0873edbc6a..a001e1ce404 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -118,18 +118,12 @@ boot_warm:
 	ori	r3, r3, 0x02010000@l
 	stw	r3, 0x54(r4)
 
-#if defined(CFG_LOWBOOT08)
-	lis	r3,     0xff800160@h
-	ori	r3, r3, 0xff800160@l
-#endif
-#if defined(CFG_LOWBOOT16)
-	lis	r3,     0xff000160@h
-	ori	r3, r3, 0xff000160@l
-#endif
+	lis     r3,	lowboot_reentry@h
+	ori     r3, r3, lowboot_reentry@l
 	mtlr	r3
-	blr
-lowboot_reentry:	/* FLASH_BASE + 0x160 */
-	
+	blr				/* jump to flash based address */
+
+lowboot_reentry:
 	lis	r3,     0x0000FF00@h
 	ori	r3, r3, 0x0000FF00@l
 	stw	r3, 0x4c(r4)
@@ -143,7 +137,7 @@ lowboot_reentry:	/* FLASH_BASE + 0x160 */
 	ori	r3, r3, 0x02000001@l
 	stw	r3, 0x54(r4)
 #endif	/* CFG_LOWBOOT */
-	
+
 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
 	lis	r3, CFG_MBAR@h
 	ori	r3, r3, CFG_MBAR@l
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 12ef82b8682..38155375573 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -160,7 +160,7 @@ unsigned long measure_gclk(void)
 	timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
 	immr->im_sit.sit_piscr &= ~PISCR_PTE;
 
-#ifdef CONFIG_MPC866_et_al
+#if defined(CONFIG_MPC866_et_al)
 	/* not using OSCM, using XIN, so scale appropriately */
 	return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
 #else
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 1a9ae9d7d1f..974797f4d56 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -92,7 +92,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 
 	/* decrementer is automatically reloaded */
 	*decrementer_count = 0;
-	
+
 	/*
 	 * Mark all irqs as free
 	 */