diff options
| author | Stefan Roese <sr@denx.de> | 2007-08-18 14:33:02 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-18 14:33:02 +0200 |
| commit | 8280f6a1c43247616b68224675188e5ccd124650 (patch) | |
| tree | 1bfd0f89a9fd5c69e5b717bb7746068dd426e495 /cpu | |
| parent | 4a442d3186b31893b4f77c6e82f63c4517a5224b (diff) | |
Coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mcf523x/cpu_init.c | 30 | ||||
| -rw-r--r-- | cpu/mcf523x/speed.c | 3 | ||||
| -rw-r--r-- | cpu/mcf52x2/cpu_init.c | 2 |
3 files changed, 18 insertions, 17 deletions
diff --git a/cpu/mcf523x/cpu_init.c b/cpu/mcf523x/cpu_init.c index a31054d9ad..55c9cd356d 100644 --- a/cpu/mcf523x/cpu_init.c +++ b/cpu/mcf523x/cpu_init.c @@ -127,19 +127,19 @@ int cpu_init_r(void) void uart_port_conf(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - - /* Setup Ports: */ - switch (CFG_UART_PORT) { - case 0: - gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); - break; - case 1: - gpio->par_uart = - (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); - break; - case 2: - gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); - break; - } + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD); + break; + case 1: + gpio->par_uart = + (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD); + break; + case 2: + gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD); + break; + } } diff --git a/cpu/mcf523x/speed.c b/cpu/mcf523x/speed.c index 509109d0ed..247d3188bb 100644 --- a/cpu/mcf523x/speed.c +++ b/cpu/mcf523x/speed.c @@ -41,8 +41,9 @@ int get_clocks(void) pll->syncr = PLL_SYNCR_MFD(1); while (!(pll->synsr & PLL_SYNSR_LOCK)); - + gd->bus_clk = CFG_CLK; gd->cpu_clk = (gd->bus_clk * 2); + return (0); } diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c index f41d77bc59..458b85ef14 100644 --- a/cpu/mcf52x2/cpu_init.c +++ b/cpu/mcf52x2/cpu_init.c @@ -63,7 +63,7 @@ void cpu_init_f(void) mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ mbar2_writeByte(MCFSIM_SPURVEC, 0x00); - /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); *//* Enable a 1 cycle pre-drive cycle on CS1 */ + /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ /* * Setup chip selects... |