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authorMarian Balakowicz <m8@semihalf.com>2006-07-06 21:17:24 +0200
committerMarian Balakowicz <m8@semihalf.com>2006-07-06 21:17:24 +0200
commitedd6cf20e1be63f84e0f5af0280473cf31f0e86c (patch)
treeab7783230633c42b703e898ed09f129a386dc6eb /cpu
parentcaaeaf925fe15f46c1d5c85c37330029c86e0f39 (diff)
Fix timer problems on AMCC yucca board.
Set Timer Clock Select to use CPU clock as a timer input source.
Diffstat (limited to 'cpu')
-rw-r--r--cpu/ppc4xx/start.S8
1 files changed, 3 insertions, 5 deletions
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 17d3aa32ed1..0a6f81de449 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -158,7 +158,7 @@ _start_440:
/*----------------------------------------------------------------+
| Core bug fix. Clear the esr
+-----------------------------------------------------------------*/
- addi r0,r0,0x0000
+ li r0,0
mtspr esr,r0
/*----------------------------------------------------------------*/
/* Clear and set up some registers. */
@@ -217,17 +217,15 @@ _start_440:
| g. FCOM: Normal operation
| h. MMUPEI: Record even parity. Normal operation.
| i. FFF: Flush only as much data as necessary.
- | j. TCS: Timebase increments from externally supplied clock
+ | j. TCS: Timebase increments from CPU clock.
+-----------------------------------------------------------------*/
- addis r0, r0, 0x0000
- ori r0, r0, 0x0080
+ li r0,0
mtspr ccr1, r0
/*----------------------------------------------------------------+
| Reset the timebase.
| The previous write to CCR1 sets the timebase source.
+-----------------------------------------------------------------*/
- addi r0, r0, 0x0000
mtspr tbl, r0
mtspr tbu, r0
#endif