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authorKumar Gala <galak@kernel.crashing.org>2008-01-08 01:22:21 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-01-09 16:25:04 -0600
commitb009f3eca99bb7b9e6ba6639a8909a138dd5e9fe (patch)
tree4346cd75759fe027b7d6871e54965871efd80f94 /cpu
parentb964e9368f45372aaf1da0c13fe56f6d81ae8e96 (diff)
85xx: Remove cache config from configs.h
Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/start.S9
1 files changed, 7 insertions, 2 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index b769ef8a76a..b489d2ff0ca 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -268,7 +268,10 @@ _start_e500:
*/
lis r3,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
- li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
+ mfspr r2, L1CFG0
+ andi. r2, r2, 0x1ff
+ /* cache size * 1024 / (2 * L1 line size) */
+ slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
mtctr r2
li r0,0
1:
@@ -1061,7 +1064,9 @@ unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
- li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
+ mfspr r4,L1CFG0
+ andi. r4,r4,0x1ff
+ slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: icbi r0,r3
dcbi r0,r3