ENGR00181337-1 i.mx6 : add initial support for i.mx6sl

This patch is to add the initial support for Freescale i.mx6sl chip.
i.mx6sl is the SoloLite verison of Freescale i.mx6 family.

The patch does:
	- memory layout support,
	- iomux support,
	- clock support,

Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ryan QIAN <b32804@freescale.com>
Signed-off-by: Fugang Duan  <B38611@freescale.com>

2 files changed, 95 insertions, 9 deletions

diff --git a/cpu/arm_cortexa8/mx6/crm_regs.h b/cpu/arm_cortexa8/mx6/crm_regs.h
index 71e249b004..9a5a2b955f 100644
--- a/cpu/arm_cortexa8/mx6/crm_regs.h
+++ b/cpu/arm_cortexa8/mx6/crm_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -160,6 +160,8 @@
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK		(0x3 << 10)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET		(10)
 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			(0x3F)
+/* On SoloLite */
+#define MXC_CCM_CSCMR1_PERCLK_SEL			(1 << 6)
 
 /* Define the bits in register CSCMR2 */
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK		(0x3 << 19)
@@ -168,6 +170,9 @@
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(1 << 10)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK			(0x3F << 2)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		(2)
+/* On SoloLite */
+#define MXC_CCM_CSCMR2_EXTAUDIO_CLK_SEL_MASK		(0x3 << 19)
+#define MXC_CCM_CSCMR2_EXTAUDIO_CLK_SEL_OFFSET		19
 
 /* Define the bits in register CSCDR1 */
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK		(0x7 << 25)
@@ -186,6 +191,8 @@
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK		(0x3 << 6)
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK		(0x3F)
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET		(0)
+/* On Sololite */
+#define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
 
 /* Define the bits in register CS1CDR */
 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK		(0x3F << 25)
@@ -198,6 +205,11 @@
 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET		(6)
 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK		(0x3F)
 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET		(0)
+/* On SoloLite */
+#define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PODF_MASK		(0x7 << 25)
+#define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PODF_OFFSET		25
+#define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PRED_MASK		(0x7 << 9)
+#define MXC_CCM_CS1CDR_EXTAUDIO_CLK_PRED_OFFSET		9
 
 /* Define the bits in register CS2CDR */
 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK		(0x3F << 21)
@@ -231,6 +243,10 @@
 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET		(9)
 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK		(0x3 << 7)
 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET		(7)
+/* On SoloLite */
+#define MXC_CCM_CDCDR_MSHC_XMSCKI_PODF_MASK		(0x7 << 29)
+#define MXC_CCM_CDCDR_MSHC_XMSCKI_PODF_OFFSET		29
+#define MXC_CCM_CDCDR_MSHC_XMSCLI_CLK_SEL		(0x1 << 28)
 
 /* Define the bits in register CHSCCDR */
 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
@@ -245,6 +261,19 @@
 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET		(3)
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET		(0)
+/* On Sololite */
+#define MXC_CCM_CHSCCDR_EPDC_AXI_PRE_CLK_SEL_MASK	(0x7 << 15)
+#define MXC_CCM_CHSCCDR_EPDC_AXI_PRE_CLK_SEL_OFFSET	15
+#define MXC_CCM_CHSCCDR_EPDC_AXI_PODF_MASK		(0x7 << 12)
+#define MXC_CCM_CHSCCDR_EPDC_AXI_PODF_OFFSET		12
+#define MXC_CCM_CHSCCDR_EPDC_AXI_CLK_SEL_MASK		(0x7 << 9)
+#define MXC_CCM_CHSCCDR_EPDC_AXI_CLK_SEL_OFFSET		9
+#define MXC_CCM_CHSCCDR_PXP_AXI_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define MXC_CCM_CHSCCDR_PXP_AXI_PRE_CLK_SEL_OFFSET	6
+#define MXC_CCM_CHSCCDR_PXP_AXI_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CHSCCDR_PXP_AXI_PODF_OFFSET		3
+#define MXC_CCM_CHSCCDR_PXP_AXI_CLK_SEL_MASK		0x7
+#define MXC_CCM_CHSCCDR_PXP_AXI_CLK_SEL_OFFSET		0
 
 /* Define the bits in register CSCDR2 */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK		(0x3F << 19)
@@ -261,6 +290,20 @@
 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET		(3)
 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK		(0x7)
 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET		(0)
+/* On SoloLite */
+#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL			(0x1 << 18)
+#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL_MASK	(0x7 << 15)
+#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_CLK_SEL_OFFSET	15
+#define MXC_CCM_CSCDR2_EPDC_PIX_PODF_MASK		(0x7 << 12)
+#define MXC_CCM_CSCDR2_EPDC_PIX_PODF_OFFSET		12
+#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_MASK		(0X7 << 9)
+#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_OFFSET		9
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL_MASK	(0x7 << 6)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_CLK_SEL_OFFSET	6
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PODF_MASK		(0x7 << 3)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PODF_OFFSET		3
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK		0x7
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET		0
 
 /* Define the bits in register CSCDR3 */
 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK		(0x7 << 16)
@@ -291,7 +334,7 @@
 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS		(1 << 21)
 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS		(1 << 19)
 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM			(1 << 17)
-#define MXC_CCM_CLPCR_WB_PER_AT_LPM			(1 << 17)
+#define MXC_CCM_CLPCR_WB_PER_AT_LPM			(1 << 16)
 #define MXC_CCM_CLPCR_COSC_PWRDOWN			(1 << 11)
 #define MXC_CCM_CLPCR_STBY_COUNT_MASK			(0x3 << 9)
 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET			(9)
@@ -333,16 +376,19 @@
 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET			(21)
 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET			(16)
 #define MXC_CCM_CCOSR_CKO2_SEL_MASK			(0x1F << 16)
-#define MXC_CCM_CCOSR_CKOL_EN				(0x1 << 7)
-#define MXC_CCM_CCOSR_CKOL_DIV_MASK			(0x7 << 4)
-#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET			(4)
-#define MXC_CCM_CCOSR_CKOL_SEL_MASK			(0xF)
-#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET			(0)
+#define MXC_CCM_CCOSR_CLKO2_CLKO1_SEL			(0x1 << 8)
+#define MXC_CCM_CCOSR_CKO1_EN				(0x1 << 7)
+#define MXC_CCM_CCOSR_CKO1_DIV_MASK			(0x7 << 4)
+#define MXC_CCM_CCOSR_CKO1_DIV_OFFSET			(4)
+#define MXC_CCM_CCOSR_CKO1_SEL_MASK			(0xF)
+#define MXC_CCM_CCOSR_CKO1_SEL_OFFSET			(0)
 
 /* Define the bits in registers CGPR */
 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE		(1 << 4)
 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS			(1 << 2)
 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER			(1)
+/* On SoloLite */
+#define MXC_CCM_CGPR_MEM_IPG_STOP_MASK			(0x1 << 1)
 
 /* Define the bits in registers CCGRx */
 #define MXC_CCM_CCGR_CG_MASK				3
diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c
index 8ec6b4334c..9294be0a41 100644
--- a/cpu/arm_cortexa8/mx6/generic.c
+++ b/cpu/arm_cortexa8/mx6/generic.c
@@ -45,8 +45,10 @@ enum pll_clocks {
 	USBOTG_PLL3,    /* OTG USB PLL */
 	AUD_PLL4,	/* Audio PLL */
 	VID_PLL5,	/* Video PLL */
+#ifndef CONFIG_MX6SL
 	MLB_PLL6,	/* MLB PLL */
 	USBHOST_PLL7,   /* Host USB PLL */
+#endif
 	ENET_PLL8,      /* ENET PLL */
 };
 
@@ -55,8 +57,8 @@ enum pll_clocks {
 /* Out-of-reset PFDs and clock source definitions */
 #define PLL2_PFD0_FREQ	352000000
 #define PLL2_PFD1_FREQ	594000000
-#define PLL2_PFD2_FREQ	400000000
-#define PLL2_PFD2_DIV_FREQ	200000000
+#define PLL2_PFD2_FREQ	396000000
+#define PLL2_PFD2_DIV_FREQ	198000000
 #define PLL3_PFD0_FREQ	720000000
 #define PLL3_PFD1_FREQ	540000000
 #define PLL3_PFD2_FREQ	508200000
@@ -126,8 +128,10 @@ static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
 		}
 	case AUD_PLL4:
 	case VID_PLL5:
+#ifndef CONFIG_MX6SL
 	case MLB_PLL6:
 	case USBHOST_PLL7:
+#endif
 	default:
 		return 0;
 	}
@@ -201,6 +205,10 @@ static u32 __get_uart_clk(void)
 	u32 freq = PLL3_80M, reg, podf;
 
 	reg = __REG(MXC_CCM_CSCDR1);
+#ifdef CONFIG_MX6SL
+	if (reg & 0x40) /* UART clock from 24M OSC */
+		freq = CONFIG_MX6_HCLK_FREQ;
+#endif
 	podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
 		MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
 	freq /= (podf + 1);
@@ -299,6 +307,35 @@ static u32 __get_nfc_clk(void)
 	return  clkroot / (pred + 1) / (podf + 1);
 }
 
+#ifdef CONFIG_MX6SL
+static u32 __get_ddr_clk(void)
+{
+	u32 cbcmr = __REG(MXC_CCM_CBCMR);
+	u32 cbcdr = __REG(MXC_CCM_CBCDR);
+	u32 freq, podf;
+
+	podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
+			>> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+
+	switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+		MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) {
+	case 0:
+		freq = __decode_pll(BUS_PLL2, CONFIG_MX6_HCLK_FREQ);
+		break;
+	case 1:
+		freq = PLL2_PFD2_FREQ;
+		break;
+	case 2:
+		freq = PLL2_PFD0_FREQ;
+		break;
+	case 3:
+		freq = PLL2_PFD2_DIV_FREQ;
+	}
+
+	return freq / (podf + 1);
+
+}
+#else
 static u32 __get_ddr_clk(void)
 {
 	u32 cbcdr = __REG(MXC_CCM_CBCDR);
@@ -307,6 +344,7 @@ static u32 __get_ddr_clk(void)
 
 	return __get_periph_clk() / (podf + 1);
 }
+#endif
 
 static u32 __get_usdhc1_clk(void)
 {
@@ -438,7 +476,9 @@ void mxc_dump_clocks(void)
 	printf("usdhc2 clock  : %dHz\n", mxc_get_clock(MXC_ESDHC2_CLK));
 	printf("usdhc3 clock  : %dHz\n", mxc_get_clock(MXC_ESDHC3_CLK));
 	printf("usdhc4 clock  : %dHz\n", mxc_get_clock(MXC_ESDHC4_CLK));
+#ifndef CONFIG_MX6SL
 	printf("nfc clock     : %dHz\n", mxc_get_clock(MXC_NFC_CLK));
+#endif
 }
 
 #ifdef CONFIG_CMD_CLOCK