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authorDave Liu <r63238@freescale.com>2007-09-18 12:37:57 +0800
committerKim Phillips <kim.phillips@freescale.com>2008-01-08 09:55:39 -0600
commit19580e660cc8da49f16536a8bd78c047c7bc12e5 (patch)
tree2b0d1681d4b61b0d7bbf5cf886d25fc3d2753ddc /cpu
parent555da61702771fe0f76f3de23b4e7590f3704161 (diff)
mpc83xx: Add the support of MPC837xEMDS board
The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc83xx/cpu_init.c6
-rw-r--r--cpu/mpc83xx/spd_sdram.c7
2 files changed, 10 insertions, 3 deletions
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 722497966a1..2b92be01ad9 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -155,6 +155,10 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CFG_DDRCDR
im->sysconf.ddrcdr = CFG_DDRCDR;
#endif
+ /* Output buffer impedance register */
+#ifdef CFG_OBIR
+ im->sysconf.obir = CFG_OBIR;
+#endif
#ifdef CONFIG_QE
/* Config QE ioports */
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index ee2d0385e45..29dd47078ec 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2006 Freescale Semiconductor, Inc.
+ * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -198,6 +198,7 @@ long int spd_sdram()
if(spd.mem_type == SPD_MEMTYPE_DDR2) {
immap->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
}
+ udelay(50000);
#endif
/*
@@ -576,7 +577,7 @@ long int spd_sdram()
if (effective_data_rate == 266 || effective_data_rate == 333) {
cpo = 0x7; /* READ_LAT + 5/4 */
} else if (effective_data_rate == 400) {
- cpo = 0x9; /* READ_LAT + 7/4 */
+ cpo = 0x7; /* READ_LAT + 5/4 */
} else {
/* Automatic calibration */
cpo = 0x1f;
@@ -705,9 +706,11 @@ long int spd_sdram()
* SDRAM Cfg 2
*/
odt_cfg = 0;
+#ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
if (odt_rd_cfg | odt_wr_cfg) {
odt_cfg = 0x2; /* ODT to IOs during reads */
}
+#endif
if (spd.mem_type == SPD_MEMTYPE_DDR2) {
ddr->sdram_cfg2 = (0
| (0 << 26) /* True DQS */