diff options
| author | Zhang Jiejing <jiejing.zhang@freescale.com> | 2011-11-23 13:49:37 +0800 |
|---|---|---|
| committer | Zhang Jiejing <jiejing.zhang@freescale.com> | 2011-11-23 14:28:45 +0800 |
| commit | 08b5c56351ea218583483f69b0c19c53a836c3c4 (patch) | |
| tree | 0bf2d364c1b6d79916305565a1a01f75aa5f09dd /cpu | |
| parent | ddbe9eb5ee0e4e91983d362d6b685ec016f68366 (diff) | |
ENGR00162938 MX5: Add download_mode command in uboot to enter MFG download mode.
Add download_mode command in uboot to enter MFG dowload mode ,
you can try download mode command in uboot and enter download mode.
it first set srtc register, then before enter linux,
it will clear these register to prevent the up comming watchdog
reset will enter mfgtool mode.
only add mx53 now.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/arm_cortexa8/cpu.c | 4 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx53/generic.c | 35 |
2 files changed, 39 insertions, 0 deletions
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index ac7ac135a54..a7a6fb79813 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -136,6 +136,10 @@ int cleanup_before_linux(void) { unsigned int i; +#ifdef CONFIG_CMD_IMX_DOWNLOAD_MODE + clear_mfgmode_mem(); +#endif + #ifdef CONFIG_VIDEO_MX5 ipu_disable_channel(MEM_BG_SYNC); ipu_uninit_channel(MEM_BG_SYNC); diff --git a/cpu/arm_cortexa8/mx53/generic.c b/cpu/arm_cortexa8/mx53/generic.c index d54bf2cf612..e53a7203529 100644 --- a/cpu/arm_cortexa8/mx53/generic.c +++ b/cpu/arm_cortexa8/mx53/generic.c @@ -1131,3 +1131,38 @@ void ipu_clk_disable(void) reg |= (0x1 << 18); writel(reg, CCM_BASE_ADDR + CLKCTL_CLPCR); } + +#ifdef CONFIG_CMD_IMX_DOWNLOAD_MODE + +/* this function should call before enter linux, otherwise, you + * watchdog reset will enter mfg download mode again, clear this bit + * to prevent this behavior */ +void clear_mfgmode_mem(void) +{ + u32 reg; + reg = readl(SRTC_BASE_ADDR + SRTC_LPGR); + reg &= ~0x12000000; + writel(reg, SRTC_BASE_ADDR + SRTC_LPGR); +} + +void do_switch_mfgmode(void) +{ + u32 reg; + reg = readl(SRTC_BASE_ADDR + SRTC_LPGR); + /* After set bit 28 of LPGR register of SRTC to 1, Set bit + * [25:0] to specified value according to format of SBMR, + * after trigger a watchdog reset, ROM will read Bit 28 and + * then copy bit [25:0] of LPGR to SBMR, then ROM can enter + * serial download mode.*/ + reg |= 0x12000000; + writel(reg, SRTC_BASE_ADDR + SRTC_LPGR); + /* this watchdog reset will let chip enter mfgtool download + * mode. */ + do_reset(NULL, 0, 0, NULL); +} + +U_BOOT_CMD( + download_mode, 1, 1, do_switch_mfgmode, + "download_mode - enter i.MX serial/usb download mode\n", + ""); +#endif |