punt Blackfin VDSP headers and import sanitized/auto-generated ones

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

34 files changed, 274 insertions, 372 deletions

diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h
index 25b96a9f693..9970b723d54 100644
--- a/cpu/bf533/bf533_serial.h
+++ b/cpu/bf533/bf533_serial.h
@@ -49,8 +49,8 @@
 #include <asm/blackfin.h>
 
 #define SYNC_ALL	__asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH	*pUART_LCR |= UART_LCR_DLAB;
-#define ACCESS_PORT_IER	*pUART_LCR &= (~UART_LCR_DLAB);
+#define ACCESS_LATCH	*pUART_LCR |= DLAB;
+#define ACCESS_PORT_IER	*pUART_LCR &= (~DLAB);
 
 void serial_setbrg(void);
 static void local_put_char(char ch);
diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S
index 03aebe4b4c5..d9015c6d1a0 100644
--- a/cpu/bf533/cache.S
+++ b/cpu/bf533/cache.S
@@ -2,6 +2,7 @@
 #include <asm/linkage.h>
 #include <config.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
 
 .text
 .align 2
@@ -11,7 +12,7 @@ ENTRY(_blackfin_icache_flush_range)
 	P0 = R2;
 	P1 = R1;
 	CSYNC;
-1:
+	1:
 	IFLUSH[P0++];
 	CC = P0 < P1(iu);
 	IF CC JUMP 1b(bp);
diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c
index 8118861f8d8..edb771e33c7 100644
--- a/cpu/bf533/cpu.c
+++ b/cpu/bf533/cpu.c
@@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2];
 
 int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
+	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
 	    );
 
 	return 0;
@@ -100,22 +100,18 @@ void icache_enable(void)
 
 	}
 
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-	sync();
-	sti();
+	SSYNC();
 }
 
 void icache_disable(void)
 {
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-	sync();
-	sti();
+	SSYNC();
 }
 
 int icache_status(void)
@@ -175,14 +171,12 @@ void dcache_enable(void)
 		}
 	}
 
-	cli();
 	temp = *(unsigned int *)DMEM_CONTROL;
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL =
 	    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
-	sync();
-	sti();
+	SSYNC();
 }
 
 void dcache_disable(void)
@@ -190,13 +184,11 @@ void dcache_disable(void)
 	unsigned int *I0, *I1;
 	int i;
 
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL &=
 	    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-	sync();
-	sti();
+	SSYNC();
 
 	/* after disable dcache,
 	 * clear it so we don't confuse the next application
diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S
index e1a8e2ff88e..67a99e46bd4 100644
--- a/cpu/bf533/init_sdram.S
+++ b/cpu/bf533/init_sdram.S
@@ -4,6 +4,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #include <asm/mem_init.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
 .global init_sdram;
 
 #if (CONFIG_CCLK_DIV == 1)
diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S
index 99ed9203287..8694ca2c2ca 100644
--- a/cpu/bf533/init_sdram_bootrom_initblock.S
+++ b/cpu/bf533/init_sdram_bootrom_initblock.S
@@ -4,6 +4,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #include <asm/mem_init.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
 .global init_sdram;
 
 #if (CONFIG_CCLK_DIV == 1)
diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S
index c356d53aa61..7556ec9fbd0 100644
--- a/cpu/bf533/interrupt.S
+++ b/cpu/bf533/interrupt.S
@@ -42,9 +42,7 @@
 #define ASSEMBLY
 #include <config.h>
 #include <asm/blackfin.h>
-#include <asm/hw_irq.h>
 #include <asm/entry.h>
-#include <asm/blackfin_defs.h>
 
 .global _blackfin_irq_panic;
 
@@ -55,7 +53,7 @@
 .global _evt_emulation
 _evt_emulation:
 	SAVE_CONTEXT
-	r0 = IRQ_EMU;
+	r0 = 0;
 	r1 = seqstat;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -66,7 +64,7 @@ _evt_emulation:
 .global _evt_nmi
 _evt_nmi:
 	SAVE_CONTEXT
-	r0 = IRQ_NMI;
+	r0 = 2;
 	r1 = RETN;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -88,7 +86,7 @@ _trap:
 .global _evt_rst
 _evt_rst:
 	SAVE_CONTEXT
-	r0 = IRQ_RST;
+	r0 = 1;
 	r1 = RETN;
 	sp += -12;
 	call _do_reset;
@@ -98,7 +96,7 @@ _evt_rst_exit:
 	rtn;
 
 irq_panic:
-	r0 = IRQ_EVX;
+	r0 = 3;
 	r1 =  sp;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -115,7 +113,7 @@ _evt_ivhw_exit:
 .global _evt_timer
 _evt_timer:
 	SAVE_CONTEXT
-	r0 = IRQ_CORETMR;
+	r0 = 6;
 	sp += -12;
 	/* Polling method used now. */
 	/* call timer_int; */
diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c
index 14d06cf8dfa..3d1c3bc8c21 100644
--- a/cpu/bf533/interrupts.c
+++ b/cpu/bf533/interrupts.c
@@ -35,8 +35,6 @@
  */
 
 #include <common.h>
-#include <asm/machdep.h>
-#include <asm/irq.h>
 #include <config.h>
 #include <asm/blackfin.h>
 #include "cpu.h"
@@ -72,12 +70,10 @@ ulong get_tbclk(void)
 
 void enable_interrupts(void)
 {
-	restore_flags(int_flag);
 }
 
 int disable_interrupts(void)
 {
-	save_and_cli(int_flag);
 	return 1;
 }
 
diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c
index 55866896a03..05d9a1b67ee 100644
--- a/cpu/bf533/ints.c
+++ b/cpu/bf533/ints.c
@@ -39,12 +39,9 @@
 #include <common.h>
 #include <linux/stddef.h>
 #include <asm/system.h>
-#include <asm/irq.h>
 #include <asm/traps.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/machdep.h>
-#include <asm/setup.h>
 #include <asm/blackfin.h>
 #include "cpu.h"
 
@@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs)
 
 void blackfin_init_IRQ(void)
 {
-	*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
-	cli();
+	*(unsigned volatile long *)(SIC_IMASK) = 0;
 #ifndef CONFIG_KGDB
-	*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
+	*(unsigned volatile long *)(EVT1) = 0x0;
 #endif
-	*(unsigned volatile long *)(EVT_NMI_ADDR) =
+	*(unsigned volatile long *)(EVT2) =
 	    (unsigned volatile long)evt_nmi;
-	*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
+	*(unsigned volatile long *)(EVT3) =
 	    (unsigned volatile long)trap;
-	*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
+	*(unsigned volatile long *)(EVT5) =
 	    (unsigned volatile long)evt_ivhw;
-	*(unsigned volatile long *)(EVT_RESET_ADDR) =
+	*(unsigned volatile long *)(EVT0) =
 	    (unsigned volatile long)evt_rst;
-	*(unsigned volatile long *)(EVT_TIMER_ADDR) =
+	*(unsigned volatile long *)(EVT6) =
 	    (unsigned volatile long)evt_timer;
-	*(unsigned volatile long *)(EVT_IVG7_ADDR) =
+	*(unsigned volatile long *)(EVT7) =
 	    (unsigned volatile long)evt_evt7;
-	*(unsigned volatile long *)(EVT_IVG8_ADDR) =
+	*(unsigned volatile long *)(EVT8) =
 	    (unsigned volatile long)evt_evt8;
-	*(unsigned volatile long *)(EVT_IVG9_ADDR) =
+	*(unsigned volatile long *)(EVT9) =
 	    (unsigned volatile long)evt_evt9;
-	*(unsigned volatile long *)(EVT_IVG10_ADDR) =
+	*(unsigned volatile long *)(EVT10) =
 	    (unsigned volatile long)evt_evt10;
-	*(unsigned volatile long *)(EVT_IVG11_ADDR) =
+	*(unsigned volatile long *)(EVT11) =
 	    (unsigned volatile long)evt_evt11;
-	*(unsigned volatile long *)(EVT_IVG12_ADDR) =
+	*(unsigned volatile long *)(EVT12) =
 	    (unsigned volatile long)evt_evt12;
-	*(unsigned volatile long *)(EVT_IVG13_ADDR) =
+	*(unsigned volatile long *)(EVT13) =
 	    (unsigned volatile long)evt_evt13;
-	*(unsigned volatile long *)(EVT_IVG14_ADDR) =
+	*(unsigned volatile long *)(EVT14) =
 	    (unsigned volatile long)evt_system_call;
-	*(unsigned volatile long *)(EVT_IVG15_ADDR) =
+	*(unsigned volatile long *)(EVT15) =
 	    (unsigned volatile long)evt_soft_int1;
 	*(volatile unsigned long *)ILAT = 0;
 	asm("csync;");
-	sti();
 	*(volatile unsigned long *)IMASK = 0xffbf;
 	asm("csync;");
 }
diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c
index 8ac6e3ff64e..05fcfcccce6 100644
--- a/cpu/bf533/serial.c
+++ b/cpu/bf533/serial.c
@@ -43,14 +43,12 @@
  */
 
 #include <common.h>
-#include <asm/irq.h>
 #include <asm/system.h>
-#include <asm/segment.h>
 #include <asm/bitops.h>
 #include <asm/delay.h>
-#include <asm/uaccess.h>
 #include <asm/io.h>
 #include "bf533_serial.h"
+#include <asm/mach-common/bits/uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -85,30 +83,30 @@ void serial_setbrg(void)
 	}
 
 	/* Enable UART */
-	*pUART_GCTL |= UART_GCTL_UCEN;
-	sync();
+	*pUART_GCTL |= UCEN;
+	SSYNC();
 
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH;
-	sync();
+	SSYNC();
 
 	*pUART_DLL = hw_baud_table[i].dl_low;
-	sync();
+	SSYNC();
 	*pUART_DLH = hw_baud_table[i].dl_high;
-	sync();
+	SSYNC();
 
 	/* Clear DLAB in LCR to Access THR RBR IER */
 	ACCESS_PORT_IER;
-	sync();
+	SSYNC();
 
 	/* Enable  ERBFI and ELSI interrupts
 	 * to poll SIC_ISR register*/
-	*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
-	sync();
+	*pUART_IER = ELSI | ERBFI | ETBEI;
+	SSYNC();
 
 	/* Set LCR to Word Lengh 8-bit word select */
-	*pUART_LCR = UART_LCR_WLS8;
-	sync();
+	*pUART_LCR = WLS_8;
+	SSYNC();
 
 	return;
 }
@@ -121,14 +119,14 @@ int serial_init(void)
 
 void serial_putc(const char c)
 {
-	if ((*pUART_LSR) & UART_LSR_TEMT) {
+	if ((*pUART_LSR) & TEMT) {
 		if (c == '\n')
 			serial_putc('\r');
 
 		local_put_char(c);
 	}
 
-	while (!((*pUART_LSR) & UART_LSR_TEMT))
+	while (!((*pUART_LSR) & TEMT))
 		SYNC_ALL;
 
 	return;
@@ -136,7 +134,7 @@ void serial_putc(const char c)
 
 int serial_tstc(void)
 {
-	if (*pUART_LSR & UART_LSR_DR)
+	if (*pUART_LSR & DR)
 		return 1;
 	else
 		return 0;
@@ -149,14 +147,14 @@ int serial_getc(void)
 	int ret;
 
 	/* Poll for RX Interrupt */
-	while (!((isr_val =
-		  *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
+	while (!serial_tstc())
+		continue;
 	asm("csync;");
 
 	uart_lsr_val = *pUART_LSR;	/* Clear status bit */
 	uart_rbr_val = *pUART_RBR;	/* getc() */
 
-	if (isr_val & IRQ_UART_ERROR_BIT) {
+	if (uart_lsr_val & (OE|PE|FE|BI)) {
 		ret = -1;
 	} else {
 		ret = uart_rbr_val & 0xff;
@@ -177,19 +175,12 @@ static void local_put_char(char ch)
 	int flags = 0;
 	unsigned long isr_val;
 
-	save_and_cli(flags);
-
 	/* Poll for TX Interruput */
-	while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
+	while (!(*pUART_LSR & THRE))
+		continue;
 	asm("csync;");
 
 	*pUART_THR = ch;	/* putc() */
 
-	if (isr_val & IRQ_UART_ERROR_BIT) {
-		printf("?");
-	}
-
-	restore_flags(flags);
-
 	return;
 }
diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S
index 67a60cf21e0..6b43b9d03af 100644
--- a/cpu/bf533/start.S
+++ b/cpu/bf533/start.S
@@ -41,6 +41,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/pll.h>
+
 .global _stext;
 .global __bss_start;
 .global start;
@@ -143,8 +147,8 @@ no_soft_reset:
 	nop;
 
 	/* Clear EVT registers */
-	p0.h = (EVT_EMULATION_ADDR >> 16);
-	p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+	p0.h = (EVT0 >> 16);
+	p0.l = (EVT0 & 0xFFFF);
 	p0 += 8;
 	p1 = 14;
 	r1 = 0;
@@ -200,8 +204,8 @@ loop1:
 	 */
 
 	/* To keep ourselves in the supervisor mode */
-	p0.l = (EVT_IVG15_ADDR & 0xFFFF);
-	p0.h = (EVT_IVG15_ADDR >> 16);
+	p0.l = (EVT15 & 0xFFFF);
+	p0.h = (EVT15 >> 16);
 
 	p1.l = _real_start;
 	p1.h = _real_start;
@@ -209,8 +213,8 @@ loop1:
 
 	p0.l = (IMASK & 0xFFFF);
 	p0.h = (IMASK >> 16);
-	r0.l = LO(IVG15_POS);
-	r0.h = HI(IVG15_POS);
+	r0.l = LO(EVT_IVG15);
+	r0.h = HI(EVT_IVG15);
 	[p0] = r0;
 	raise 15;
 	p0.l = WAIT_HERE;
@@ -236,8 +240,8 @@ copy:
 	R1.H = reset_end;
 	R1.L = reset_end;
 	R2 = R1 - R0;		/* Count */
-	R1.H = hi(L1_ISRAM);	/* Destination Address (high) */
-	R1.L = lo(L1_ISRAM);	/* Destination Address (low) */
+	R1.H = hi(L1_INST_SRAM);	/* Destination Address (high) */
+	R1.L = lo(L1_INST_SRAM);	/* Destination Address (low) */
 	R3.L = DMAEN;		/* Source DMAConfig Value (8-bit words) */
 	/* Destination DMAConfig Value (8-bit words) */
 	R4.L = (DI_EN | WNR | DMAEN);
diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c
index 19b1fde41d3..7e156d51106 100644
--- a/cpu/bf533/traps.c
+++ b/cpu/bf533/traps.c
@@ -36,14 +36,13 @@
 #include <common.h>
 #include <linux/types.h>
 #include <asm/errno.h>
-#include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/traps.h>
-#include <asm/machdep.h>
 #include "cpu.h"
-#include <asm/arch/anomaly.h>
 #include <asm/cplb.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
 
 void init_IRQ(void)
 {
@@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] =
 void trap_c(struct pt_regs *regs)
 {
 	unsigned int addr;
-	unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
+	unsigned long trapnr = (regs->seqstat) & EXCAUSE;
 	unsigned int i, j, size, *I0, *I1;
 	unsigned short data = 0;
 
@@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs)
 	/* 0x26 - Data CPLB Miss */
 	case VEC_CPLB_M:
 
-#ifdef ANOMALY_05000261
+#if ANOMALY_05000261
 		/*
 		 * Work around an anomaly: if we see a new DCPLB fault,
 		 * return without doing anything. Then,
@@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs)
 
 		/* Turn the cache off */
 		if (data) {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL &=
 			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-			sync();
+			SSYNC();
 		}
 
 		if (data) {
@@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs)
 		/* Turn the cache back on */
 		if (data) {
 			j = *(unsigned int *)DMEM_CONTROL;
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL =
 			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-			sync();
+			SSYNC();
 		}
 
 		break;
diff --git a/cpu/bf537/cache.S b/cpu/bf537/cache.S
index 5bda5bf97f7..d9015c6d1a0 100644
--- a/cpu/bf537/cache.S
+++ b/cpu/bf537/cache.S
@@ -2,6 +2,7 @@
 #include <asm/linkage.h>
 #include <config.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
 
 .text
 .align 2
diff --git a/cpu/bf537/cpu.c b/cpu/bf537/cpu.c
index 62f603bdb0f..7233908a07e 100644
--- a/cpu/bf537/cpu.c
+++ b/cpu/bf537/cpu.c
@@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2];
 
 int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
+	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
 	    );
 
 	return 0;
@@ -103,24 +103,20 @@ void icache_enable(void)
 
 	}
 
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-	sync();
-	sti();
+	SSYNC();
 }
 
 void icache_disable(void)
 {
 	if ((*pCHIPID >> 28) < 2)
 		return;
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-	sync();
-	sti();
+	SSYNC();
 }
 
 int icache_status(void)
@@ -180,14 +176,12 @@ void dcache_enable(void)
 		}
 	}
 
-	cli();
 	temp = *(unsigned int *)DMEM_CONTROL;
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL =
 	    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
-	sync();
-	sti();
+	SSYNC();
 }
 
 void dcache_disable(void)
@@ -195,13 +189,11 @@ void dcache_disable(void)
 	unsigned int *I0, *I1;
 	int i;
 
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL &=
 	    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-	sync();
-	sti();
+	SSYNC();
 
 	/* after disable dcache,
 	 * clear it so we don't confuse the next application
diff --git a/cpu/bf537/i2c.c b/cpu/bf537/i2c.c
index 0daba63b68a..ab7dd388c9d 100644
--- a/cpu/bf537/i2c.c
+++ b/cpu/bf537/i2c.c
@@ -21,53 +21,10 @@
 #include <asm/blackfin.h>
 #include <i2c.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/twi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define bfin_read16(addr) ({ unsigned __v; \
-			__asm__ __volatile__ (\
-			"%0 = w[%1] (z);\n\t"\
-			: "=d"(__v) : "a"(addr)); (unsigned short)__v; })
-
-#define bfin_write16(addr,val) ({\
-			__asm__ __volatile__ (\
-			"w[%0] = %1;\n\t"\
-			: : "a"(addr) , "d"(val) : "memory");})
-
-/* Two-Wire Interface		(0xFFC01400 - 0xFFC014FF) */
-#define bfin_read_TWI_CLKDIV()		bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)	bfin_write16(TWI_CLKDIV,val)
-#define bfin_read_TWI_CONTROL()		bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val)	bfin_write16(TWI_CONTROL,val)
-#define bfin_read_TWI_SLAVE_CTL()	bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val)	bfin_write16(TWI_SLAVE_CTL,val)
-#define bfin_read_TWI_SLAVE_STAT()	bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val)	bfin_write16(TWI_SLAVE_STAT,val)
-#define bfin_read_TWI_SLAVE_ADDR()	bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val)	bfin_write16(TWI_SLAVE_ADDR,val)
-#define bfin_read_TWI_MASTER_CTL()	bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val)	bfin_write16(TWI_MASTER_CTL,val)
-#define bfin_read_TWI_MASTER_STAT()	bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val)	bfin_write16(TWI_MASTER_STAT,val)
-#define bfin_read_TWI_MASTER_ADDR()	bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val)	bfin_write16(TWI_MASTER_ADDR,val)
-#define bfin_read_TWI_INT_STAT()	bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)	bfin_write16(TWI_INT_STAT,val)
-#define bfin_read_TWI_INT_MASK()	bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)	bfin_write16(TWI_INT_MASK,val)
-#define bfin_read_TWI_FIFO_CTL()	bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val)	bfin_write16(TWI_FIFO_CTL,val)
-#define bfin_read_TWI_FIFO_STAT()	bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)	bfin_write16(TWI_FIFO_STAT,val)
-#define bfin_read_TWI_XMT_DATA8()	bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)	bfin_write16(TWI_XMT_DATA8,val)
-#define bfin_read_TWI_XMT_DATA16()	bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val)	bfin_write16(TWI_XMT_DATA16,val)
-#define bfin_read_TWI_RCV_DATA8()	bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)	bfin_write16(TWI_RCV_DATA8,val)
-#define bfin_read_TWI_RCV_DATA16()	bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val)	bfin_write16(TWI_RCV_DATA16,val)
-
 #ifdef DEBUG_I2C
 #define PRINTD(fmt,args...)	do {	\
 	if (gd->have_console)		\
diff --git a/cpu/bf537/init_sdram.S b/cpu/bf537/init_sdram.S
index 897a5890ed1..e9975000a28 100644
--- a/cpu/bf537/init_sdram.S
+++ b/cpu/bf537/init_sdram.S
@@ -4,6 +4,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #include <asm/mem_init.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
 .global init_sdram;
 
 #if (BFIN_BOOT_MODE != BF537_UART_BOOT)
diff --git a/cpu/bf537/init_sdram_bootrom_initblock.S b/cpu/bf537/init_sdram_bootrom_initblock.S
index f9adbb97155..197b8360677 100644
--- a/cpu/bf537/init_sdram_bootrom_initblock.S
+++ b/cpu/bf537/init_sdram_bootrom_initblock.S
@@ -4,6 +4,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #include <asm/mem_init.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
 .global init_sdram;
 
 #if (BFIN_BOOT_MODE != BF537_UART_BOOT)
diff --git a/cpu/bf537/interrupt.S b/cpu/bf537/interrupt.S
index a71df55a938..fe850bf2e3a 100644
--- a/cpu/bf537/interrupt.S
+++ b/cpu/bf537/interrupt.S
@@ -42,9 +42,7 @@
 #define ASSEMBLY
 #include <config.h>
 #include <asm/blackfin.h>
-#include <asm/hw_irq.h>
 #include <asm/entry.h>
-#include <asm/blackfin_defs.h>
 
 .global _blackfin_irq_panic;
 
@@ -55,7 +53,7 @@
 .global _evt_emulation
 _evt_emulation:
 	SAVE_CONTEXT
-	r0 = IRQ_EMU;
+	r0 = 0;
 	r1 = seqstat;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -66,7 +64,7 @@ _evt_emulation:
 .global _evt_nmi
 _evt_nmi:
 	SAVE_CONTEXT
-	r0 = IRQ_NMI;
+	r0 = 2;
 	r1 = RETN;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -88,7 +86,7 @@ _trap:
 .global _evt_rst
 _evt_rst:
 	SAVE_CONTEXT
-	r0 = IRQ_RST;
+	r0 = 1;
 	r1 = RETN;
 	sp += -12;
 	call _do_reset;
@@ -98,7 +96,7 @@ _evt_rst_exit:
 	rtn;
 
 irq_panic:
-	r0 = IRQ_EVX;
+	r0 = 3;
 	r1 =  sp;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -115,7 +113,7 @@ _evt_ivhw_exit:
 .global _evt_timer
 _evt_timer:
 	SAVE_CONTEXT
-	r0 = IRQ_CORETMR;
+	r0 = 6;
 	sp += -12;
 	/* Polling method used now. */
 	/* call timer_int; */
diff --git a/cpu/bf537/interrupts.c b/cpu/bf537/interrupts.c
index d2213b11568..853fa492c75 100644
--- a/cpu/bf537/interrupts.c
+++ b/cpu/bf537/interrupts.c
@@ -35,8 +35,6 @@
  */
 
 #include <common.h>
-#include <asm/machdep.h>
-#include <asm/irq.h>
 #include <config.h>
 #include <asm/blackfin.h>
 #include "cpu.h"
@@ -72,12 +70,10 @@ ulong get_tbclk (void)
 
 void enable_interrupts(void)
 {
-	restore_flags(int_flag);
 }
 
 int disable_interrupts(void)
 {
-	save_and_cli(int_flag);
 	return 1;
 }
 
diff --git a/cpu/bf537/ints.c b/cpu/bf537/ints.c
index 55866896a03..05d9a1b67ee 100644
--- a/cpu/bf537/ints.c
+++ b/cpu/bf537/ints.c
@@ -39,12 +39,9 @@
 #include <common.h>
 #include <linux/stddef.h>
 #include <asm/system.h>
-#include <asm/irq.h>
 #include <asm/traps.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/machdep.h>
-#include <asm/setup.h>
 #include <asm/blackfin.h>
 #include "cpu.h"
 
@@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs)
 
 void blackfin_init_IRQ(void)
 {
-	*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
-	cli();
+	*(unsigned volatile long *)(SIC_IMASK) = 0;
 #ifndef CONFIG_KGDB
-	*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
+	*(unsigned volatile long *)(EVT1) = 0x0;
 #endif
-	*(unsigned volatile long *)(EVT_NMI_ADDR) =
+	*(unsigned volatile long *)(EVT2) =
 	    (unsigned volatile long)evt_nmi;
-	*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
+	*(unsigned volatile long *)(EVT3) =
 	    (unsigned volatile long)trap;
-	*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
+	*(unsigned volatile long *)(EVT5) =
 	    (unsigned volatile long)evt_ivhw;
-	*(unsigned volatile long *)(EVT_RESET_ADDR) =
+	*(unsigned volatile long *)(EVT0) =
 	    (unsigned volatile long)evt_rst;
-	*(unsigned volatile long *)(EVT_TIMER_ADDR) =
+	*(unsigned volatile long *)(EVT6) =
 	    (unsigned volatile long)evt_timer;
-	*(unsigned volatile long *)(EVT_IVG7_ADDR) =
+	*(unsigned volatile long *)(EVT7) =
 	    (unsigned volatile long)evt_evt7;
-	*(unsigned volatile long *)(EVT_IVG8_ADDR) =
+	*(unsigned volatile long *)(EVT8) =
 	    (unsigned volatile long)evt_evt8;
-	*(unsigned volatile long *)(EVT_IVG9_ADDR) =
+	*(unsigned volatile long *)(EVT9) =
 	    (unsigned volatile long)evt_evt9;
-	*(unsigned volatile long *)(EVT_IVG10_ADDR) =
+	*(unsigned volatile long *)(EVT10) =
 	    (unsigned volatile long)evt_evt10;
-	*(unsigned volatile long *)(EVT_IVG11_ADDR) =
+	*(unsigned volatile long *)(EVT11) =
 	    (unsigned volatile long)evt_evt11;
-	*(unsigned volatile long *)(EVT_IVG12_ADDR) =
+	*(unsigned volatile long *)(EVT12) =
 	    (unsigned volatile long)evt_evt12;
-	*(unsigned volatile long *)(EVT_IVG13_ADDR) =
+	*(unsigned volatile long *)(EVT13) =
 	    (unsigned volatile long)evt_evt13;
-	*(unsigned volatile long *)(EVT_IVG14_ADDR) =
+	*(unsigned volatile long *)(EVT14) =
 	    (unsigned volatile long)evt_system_call;
-	*(unsigned volatile long *)(EVT_IVG15_ADDR) =
+	*(unsigned volatile long *)(EVT15) =
 	    (unsigned volatile long)evt_soft_int1;
 	*(volatile unsigned long *)ILAT = 0;
 	asm("csync;");
-	sti();
 	*(volatile unsigned long *)IMASK = 0xffbf;
 	asm("csync;");
 }
diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c
index f7a2483ffbe..3c6a37016db 100644
--- a/cpu/bf537/serial.c
+++ b/cpu/bf537/serial.c
@@ -43,14 +43,12 @@
  */
 
 #include <common.h>
-#include <asm/irq.h>
 #include <asm/system.h>
-#include <asm/segment.h>
 #include <asm/bitops.h>
 #include <asm/delay.h>
-#include <asm/uaccess.h>
 #include <asm/io.h>
 #include "serial.h"
+#include <asm/mach-common/bits/uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -85,30 +83,30 @@ void serial_setbrg(void)
 	}
 
 	/* Enable UART */
-	*pUART_GCTL |= UART_GCTL_UCEN;
-	sync();
+	*pUART0_GCTL |= UCEN;
+	SSYNC();
 
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH;
-	sync();
+	SSYNC();
 
-	*pUART_DLL = hw_baud_table[i].dl_low;
-	sync();
-	*pUART_DLH = hw_baud_table[i].dl_high;
-	sync();
+	*pUART0_DLL = hw_baud_table[i].dl_low;
+	SSYNC();
+	*pUART0_DLH = hw_baud_table[i].dl_high;
+	SSYNC();
 
 	/* Clear DLAB in LCR to Access THR RBR IER */
 	ACCESS_PORT_IER;
-	sync();
+	SSYNC();
 
 	/* Enable  ERBFI and ELSI interrupts
 	 * to poll SIC_ISR register*/
-	*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
-	sync();
+	*pUART0_IER = ELSI | ERBFI | ETBEI;
+	SSYNC();
 
 	/* Set LCR to Word Lengh 8-bit word select */
-	*pUART_LCR = UART_LCR_WLS8;
-	sync();
+	*pUART0_LCR = WLS_8;
+	SSYNC();
 
 	return;
 }
@@ -121,14 +119,14 @@ int serial_init(void)
 
 void serial_putc(const char c)
 {
-	if ((*pUART_LSR) & UART_LSR_TEMT) {
+	if ((*pUART0_LSR) & TEMT) {
 		if (c == '\n')
 			serial_putc('\r');
 
 		local_put_char(c);
 	}
 
-	while (!((*pUART_LSR) & UART_LSR_TEMT))
+	while (!((*pUART0_LSR) & TEMT))
 		SYNC_ALL;
 
 	return;
@@ -136,7 +134,7 @@ void serial_putc(const char c)
 
 int serial_tstc(void)
 {
-	if (*pUART_LSR & UART_LSR_DR)
+	if (*pUART0_LSR & DR)
 		return 1;
 	else
 		return 0;
@@ -149,14 +147,14 @@ int serial_getc(void)
 	int ret;
 
 	/* Poll for RX Interrupt */
-	while (!((isr_val =
-		  *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
+	while (!serial_tstc())
+		continue;
 	asm("csync;");
 
-	uart_lsr_val = *pUART_LSR;	/* Clear status bit */
-	uart_rbr_val = *pUART_RBR;	/* getc() */
+	uart_lsr_val = *pUART0_LSR;	/* Clear status bit */
+	uart_rbr_val = *pUART0_RBR;	/* getc() */
 
-	if (isr_val & IRQ_UART_ERROR_BIT) {
+	if (uart_lsr_val & (OE|PE|FE|BI)) {
 		ret = -1;
 	} else {
 		ret = uart_rbr_val & 0xff;
@@ -177,19 +175,12 @@ static void local_put_char(char ch)
 	int flags = 0;
 	unsigned long isr_val;
 
-	save_and_cli(flags);
-
 	/* Poll for TX Interruput */
-	while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
+	while (!(*pUART0_LSR & THRE))
+		continue;
 	asm("csync;");
 
-	*pUART_THR = ch;	/* putc() */
-
-	if (isr_val & IRQ_UART_ERROR_BIT) {
-		printf("?");
-	}
-
-	restore_flags(flags);
+	*pUART0_THR = ch;	/* putc() */
 
 	return;
 }
diff --git a/cpu/bf537/serial.h b/cpu/bf537/serial.h
index 76555c279db..e4e0b9aec6b 100644
--- a/cpu/bf537/serial.h
+++ b/cpu/bf537/serial.h
@@ -49,8 +49,8 @@
 #include <asm/blackfin.h>
 
 #define SYNC_ALL	__asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH	*pUART_LCR |= UART_LCR_DLAB;
-#define ACCESS_PORT_IER	*pUART_LCR &= (~UART_LCR_DLAB);
+#define ACCESS_LATCH	*pUART0_LCR |= DLAB;
+#define ACCESS_PORT_IER	*pUART0_LCR &= (~DLAB);
 
 void serial_setbrg(void);
 static void local_put_char(char ch);
diff --git a/cpu/bf537/start.S b/cpu/bf537/start.S
index 4e02bcb9e52..d080426ec10 100644
--- a/cpu/bf537/start.S
+++ b/cpu/bf537/start.S
@@ -41,6 +41,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/pll.h>
+
 .global _stext;
 .global __bss_start;
 .global start;
@@ -151,8 +155,8 @@ no_soft_reset:
 	nop;
 
 	/* Clear EVT registers */
-	p0.h = (EVT_EMULATION_ADDR >> 16);
-	p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+	p0.h = (EVT0 >> 16);
+	p0.l = (EVT0 & 0xFFFF);
 	p0 += 8;
 	p1 = 14;
 	r1 = 0;
@@ -291,8 +295,8 @@ postcopy:
 	R1.H = (CFG_FLASH_BASE >> 16);
 	R1.L = (CFG_FLASH_BASE & 0xFFFF);
 	R0 = R0 + R1;		/* Source Address */
-	R1.H = hi(L1_ISRAM);    /* Destination Address (high) */
-	R1.L = lo(L1_ISRAM);    /* Destination Address (low) */
+	R1.H = hi(L1_INST_SRAM);    /* Destination Address (high) */
+	R1.L = lo(L1_INST_SRAM);    /* Destination Address (low) */
 	R3.L = DMAEN;           /* Source DMAConfig Value (8-bit words) */
 	/* Destination DMAConfig Value (8-bit words) */
 	R4.L = (DI_EN | WNR | DMAEN);
@@ -415,8 +419,8 @@ loop1:
 	 */
 
 	/* To keep ourselves in the supervisor mode */
-	p0.l = (EVT_IVG15_ADDR & 0xFFFF);
-	p0.h = (EVT_IVG15_ADDR >> 16);
+	p0.l = (EVT15 & 0xFFFF);
+	p0.h = (EVT15 >> 16);
 
 	p1.l = _real_start;
 	p1.h = _real_start;
@@ -424,8 +428,8 @@ loop1:
 
 	p0.l = (IMASK & 0xFFFF);
 	p0.h = (IMASK >> 16);
-	r0.l = LO(IVG15_POS);
-	r0.h = HI(IVG15_POS);
+	r0.l = LO(EVT_IVG15);
+	r0.h = HI(EVT_IVG15);
 	[p0] = r0;
 	raise 15;
 	p0.l = WAIT_HERE;
@@ -495,8 +499,8 @@ copy:
 	R1.H = reset_end;
 	R1.L = reset_end;
 	R2 = R1 - R0;		/* Count */
-	R1.H = hi(L1_ISRAM);	/* Destination Address (high) */
-	R1.L = lo(L1_ISRAM);	/* Destination Address (low) */
+	R1.H = hi(L1_INST_SRAM);	/* Destination Address (high) */
+	R1.L = lo(L1_INST_SRAM);	/* Destination Address (low) */
 	R3.L = DMAEN;		/* Source DMAConfig Value (8-bit words) */
 	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
 
diff --git a/cpu/bf537/traps.c b/cpu/bf537/traps.c
index 4e18e27df44..51de322aed4 100644
--- a/cpu/bf537/traps.c
+++ b/cpu/bf537/traps.c
@@ -36,14 +36,13 @@
 #include <common.h>
 #include <linux/types.h>
 #include <asm/errno.h>
-#include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/traps.h>
-#include <asm/machdep.h>
 #include "cpu.h"
-#include <asm/arch/anomaly.h>
 #include <asm/cplb.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
 
 void init_IRQ(void)
 {
@@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] =
 void trap_c(struct pt_regs *regs)
 {
 	unsigned int addr;
-	unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
+	unsigned long trapnr = (regs->seqstat) & EXCAUSE;
 	unsigned int i, j, size, *I0, *I1;
 	unsigned short data = 0;
 
@@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs)
 		/* 0x26 - Data CPLB Miss */
 	case VEC_CPLB_M:
 
-#ifdef ANOMALY_05000261
+#if ANOMALY_05000261
 		/*
 		 * Work around an anomaly: if we see a new DCPLB fault,
 		 * return without doing anything. Then,
@@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs)
 
 		/* Turn the cache off */
 		if (data) {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL &=
 			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-			sync();
+			SSYNC();
 		}
 
 		if (data) {
@@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs)
 		/* Turn the cache back on */
 		if (data) {
 			j = *(unsigned int *)DMEM_CONTROL;
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL =
 			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-			sync();
+			SSYNC();
 		}
 
 		break;
diff --git a/cpu/bf561/cache.S b/cpu/bf561/cache.S
index 5bda5bf97f7..d9015c6d1a0 100644
--- a/cpu/bf561/cache.S
+++ b/cpu/bf561/cache.S
@@ -2,6 +2,7 @@
 #include <asm/linkage.h>
 #include <config.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
 
 .text
 .align 2
diff --git a/cpu/bf561/cpu.c b/cpu/bf561/cpu.c
index 5b907cd1ef2..e0dd2f5ea8d 100644
--- a/cpu/bf561/cpu.c
+++ b/cpu/bf561/cpu.c
@@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2];
 
 int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
+	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
 	    );
 
 	return 0;
@@ -100,22 +100,18 @@ void icache_enable(void)
 
 	}
 
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-	sync();
-	sti();
+	SSYNC();
 }
 
 void icache_disable(void)
 {
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-	sync();
-	sti();
+	SSYNC();
 }
 
 int icache_status(void)
@@ -175,14 +171,12 @@ void dcache_enable(void)
 		}
 	}
 
-	cli();
 	temp = *(unsigned int *)DMEM_CONTROL;
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL =
 	    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
-	sync();
-	sti();
+	SSYNC();
 }
 
 void dcache_disable(void)
@@ -191,13 +185,11 @@ void dcache_disable(void)
 	unsigned int *I0, *I1;
 	int i;
 
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL &=
 	    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-	sync();
-	sti();
+	SSYNC();
 
 	/* after disable dcache, clear it so we don't confuse the next application */
 	I0 = (unsigned int *)DCPLB_ADDR0;
diff --git a/cpu/bf561/init_sdram.S b/cpu/bf561/init_sdram.S
index d763f274f94..f5ccf30f9ab 100644
--- a/cpu/bf561/init_sdram.S
+++ b/cpu/bf561/init_sdram.S
@@ -4,6 +4,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #include <asm/mem_init.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
 .global init_sdram;
 
 #if (CONFIG_CCLK_DIV == 1)
diff --git a/cpu/bf561/init_sdram_bootrom_initblock.S b/cpu/bf561/init_sdram_bootrom_initblock.S
index 5e3c88ab6f2..9cc5e78b04d 100644
--- a/cpu/bf561/init_sdram_bootrom_initblock.S
+++ b/cpu/bf561/init_sdram_bootrom_initblock.S
@@ -4,6 +4,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #include <asm/mem_init.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
 .global init_sdram;
 
 #if (CONFIG_CCLK_DIV == 1)
diff --git a/cpu/bf561/interrupt.S b/cpu/bf561/interrupt.S
index 21839ce7de8..a10eaabe54d 100644
--- a/cpu/bf561/interrupt.S
+++ b/cpu/bf561/interrupt.S
@@ -42,9 +42,7 @@
 #define ASSEMBLY
 #include <config.h>
 #include <asm/blackfin.h>
-#include <asm/hw_irq.h>
 #include <asm/entry.h>
-#include <asm/blackfin_defs.h>
 
 .global _blackfin_irq_panic;
 
@@ -55,7 +53,7 @@
 .global _evt_emulation
 _evt_emulation:
 	SAVE_CONTEXT
-	r0 = IRQ_EMU;
+	r0 = 0;
 	r1 = seqstat;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -66,7 +64,7 @@ _evt_emulation:
 .global _evt_nmi
 _evt_nmi:
 	SAVE_CONTEXT
-	r0 = IRQ_NMI;
+	r0 = 2;
 	r1 = RETN;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -88,7 +86,7 @@ _trap:
 .global _evt_rst
 _evt_rst:
 	SAVE_CONTEXT
-	r0 = IRQ_RST;
+	r0 = 1;
 	r1 = RETN;
 	sp += -12;
 	call _do_reset;
@@ -98,7 +96,7 @@ _evt_rst_exit:
 	rtn;
 
 irq_panic:
-	r0 = IRQ_EVX;
+	r0 = 3;
 	r1 =  sp;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -115,7 +113,7 @@ _evt_ivhw_exit:
 .global _evt_timer
 _evt_timer:
 	SAVE_CONTEXT
-	r0 = IRQ_CORETMR;
+	r0 = 6;
 	sp += -12;
 	/* Polling method used now. */
 	/* call timer_int; */
diff --git a/cpu/bf561/interrupts.c b/cpu/bf561/interrupts.c
index ecbc6addfc7..78800611a3c 100644
--- a/cpu/bf561/interrupts.c
+++ b/cpu/bf561/interrupts.c
@@ -35,8 +35,6 @@
  */
 
 #include <common.h>
-#include <asm/machdep.h>
-#include <asm/irq.h>
 #include <config.h>
 #include <asm/blackfin.h>
 #include "cpu.h"
@@ -72,12 +70,10 @@ ulong get_tbclk(void)
 
 void enable_interrupts(void)
 {
-	restore_flags(int_flag);
 }
 
 int disable_interrupts(void)
 {
-	save_and_cli(int_flag);
 	return 1;
 }
 
diff --git a/cpu/bf561/ints.c b/cpu/bf561/ints.c
index 27a38a3493a..d6aa3931704 100644
--- a/cpu/bf561/ints.c
+++ b/cpu/bf561/ints.c
@@ -39,12 +39,9 @@
 #include <common.h>
 #include <linux/stddef.h>
 #include <asm/system.h>
-#include <asm/irq.h>
 #include <asm/traps.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/machdep.h>
-#include <asm/setup.h>
 #include <asm/blackfin.h>
 #include "cpu.h"
 
@@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs)
 
 void blackfin_init_IRQ(void)
 {
-	*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
-	cli();
+	*(unsigned volatile long *)(SICA_IMASK0) = 0;
 #ifndef CONFIG_KGDB
-	*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
+	*(unsigned volatile long *)(EVT1) = 0x0;
 #endif
-	*(unsigned volatile long *)(EVT_NMI_ADDR) =
+	*(unsigned volatile long *)(EVT2) =
 	    (unsigned volatile long)evt_nmi;
-	*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
+	*(unsigned volatile long *)(EVT3) =
 	    (unsigned volatile long)trap;
-	*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
+	*(unsigned volatile long *)(EVT5) =
 	    (unsigned volatile long)evt_ivhw;
-	*(unsigned volatile long *)(EVT_RESET_ADDR) =
+	*(unsigned volatile long *)(EVT0) =
 	    (unsigned volatile long)evt_rst;
-	*(unsigned volatile long *)(EVT_TIMER_ADDR) =
+	*(unsigned volatile long *)(EVT6) =
 	    (unsigned volatile long)evt_timer;
-	*(unsigned volatile long *)(EVT_IVG7_ADDR) =
+	*(unsigned volatile long *)(EVT7) =
 	    (unsigned volatile long)evt_evt7;
-	*(unsigned volatile long *)(EVT_IVG8_ADDR) =
+	*(unsigned volatile long *)(EVT8) =
 	    (unsigned volatile long)evt_evt8;
-	*(unsigned volatile long *)(EVT_IVG9_ADDR) =
+	*(unsigned volatile long *)(EVT9) =
 	    (unsigned volatile long)evt_evt9;
-	*(unsigned volatile long *)(EVT_IVG10_ADDR) =
+	*(unsigned volatile long *)(EVT10) =
 	    (unsigned volatile long)evt_evt10;
-	*(unsigned volatile long *)(EVT_IVG11_ADDR) =
+	*(unsigned volatile long *)(EVT11) =
 	    (unsigned volatile long)evt_evt11;
-	*(unsigned volatile long *)(EVT_IVG12_ADDR) =
+	*(unsigned volatile long *)(EVT12) =
 	    (unsigned volatile long)evt_evt12;
-	*(unsigned volatile long *)(EVT_IVG13_ADDR) =
+	*(unsigned volatile long *)(EVT13) =
 	    (unsigned volatile long)evt_evt13;
-	*(unsigned volatile long *)(EVT_IVG14_ADDR) =
+	*(unsigned volatile long *)(EVT14) =
 	    (unsigned volatile long)evt_system_call;
-	*(unsigned volatile long *)(EVT_IVG15_ADDR) =
+	*(unsigned volatile long *)(EVT15) =
 	    (unsigned volatile long)evt_soft_int1;
 	*(volatile unsigned long *)ILAT = 0;
 	asm("csync;");
-	sti();
 	*(volatile unsigned long *)IMASK = 0xffbf;
 	asm("csync;");
 }
diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c
index bc5a4f57260..a398fd5f84a 100644
--- a/cpu/bf561/serial.c
+++ b/cpu/bf561/serial.c
@@ -43,14 +43,12 @@
  */
 
 #include <common.h>
-#include <asm/irq.h>
 #include <asm/system.h>
-#include <asm/segment.h>
 #include <asm/bitops.h>
 #include <asm/delay.h>
-#include <asm/uaccess.h>
 #include "serial.h"
 #include <asm/io.h>
+#include <asm/mach-common/bits/uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -85,32 +83,32 @@ void serial_setbrg(void)
 	}
 
 	/* Enable UART */
-	*pUART_GCTL |= UART_GCTL_UCEN;
-	sync();
+	*pUART_GCTL |= UCEN;
+	SSYNC();
 
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH;
-	sync();
+	SSYNC();
 
 	*pUART_DLL = hw_baud_table[i].dl_low;
-	sync();
+	SSYNC();
 	*pUART_DLH = hw_baud_table[i].dl_high;
-	sync();
+	SSYNC();
 
 	/* Clear DLAB in LCR to Access THR RBR IER */
 	ACCESS_PORT_IER;
-	sync();
+	SSYNC();
 
 	/*
 	 * Enable  ERBFI and ELSI interrupts
 	 * to poll SIC_ISR register
 	 */
-	*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
-	sync();
+	*pUART_IER = ELSI | ERBFI | ETBEI;
+	SSYNC();
 
 	/* Set LCR to Word Lengh 8-bit word select */
-	*pUART_LCR = UART_LCR_WLS8;
-	sync();
+	*pUART_LCR = WLS_8;
+	SSYNC();
 
 	return;
 }
@@ -123,14 +121,14 @@ int serial_init(void)
 
 void serial_putc(const char c)
 {
-	if ((*pUART_LSR) & UART_LSR_TEMT) {
+	if ((*pUART_LSR) & TEMT) {
 		if (c == '\n')
 			serial_putc('\r');
 
 		local_put_char(c);
 	}
 
-	while (!((*pUART_LSR) & UART_LSR_TEMT))
+	while (!((*pUART_LSR) & TEMT))
 		SYNC_ALL;
 
 	return;
@@ -138,7 +136,7 @@ void serial_putc(const char c)
 
 int serial_tstc(void)
 {
-	if (*pUART_LSR & UART_LSR_DR)
+	if (*pUART_LSR & DR)
 		return 1;
 	else
 		return 0;
@@ -151,14 +149,14 @@ int serial_getc(void)
 	int ret;
 
 	/* Poll for RX Interrupt */
-	while (!((isr_val =
-		  *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
+	while (!serial_tstc())
+		continue;
 	asm("csync;");
 
 	uart_lsr_val = *pUART_LSR;	/* Clear status bit */
 	uart_rbr_val = *pUART_RBR;	/* getc() */
 
-	if (isr_val & IRQ_UART_ERROR_BIT) {
+	if (uart_lsr_val & (OE|PE|FE|BI)) {
 		ret = -1;
 	} else {
 		ret = uart_rbr_val & 0xff;
@@ -179,19 +177,12 @@ static void local_put_char(char ch)
 	int flags = 0;
 	unsigned long isr_val;
 
-	save_and_cli(flags);
-
 	/* Poll for TX Interruput */
-	while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
+	while (!(*pUART_LSR & THRE))
+		continue;
 	asm("csync;");
 
 	*pUART_THR = ch;	/* putc() */
 
-	if (isr_val & IRQ_UART_ERROR_BIT) {
-		printf("?");
-	}
-
-	restore_flags(flags);
-
 	return;
 }
diff --git a/cpu/bf561/serial.h b/cpu/bf561/serial.h
index c1cbf36acf1..647560c35c3 100644
--- a/cpu/bf561/serial.h
+++ b/cpu/bf561/serial.h
@@ -49,8 +49,8 @@
 #include <asm/blackfin.h>
 
 #define SYNC_ALL	__asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH	*pUART_LCR |= UART_LCR_DLAB;
-#define ACCESS_PORT_IER	*pUART_LCR &= (~UART_LCR_DLAB);
+#define ACCESS_LATCH	*pUART_LCR |= DLAB;
+#define ACCESS_PORT_IER	*pUART_LCR &= (~DLAB);
 
 void serial_setbrg(void);
 static void local_put_char(char ch);
diff --git a/cpu/bf561/start.S b/cpu/bf561/start.S
index bd26cf32f64..19578a52628 100644
--- a/cpu/bf561/start.S
+++ b/cpu/bf561/start.S
@@ -41,6 +41,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/pll.h>
+
 .global _stext;
 .global __bss_start;
 .global start;
@@ -127,16 +131,16 @@ no_soft_reset:
 	nop;
 
 	/* Clear EVT registers */
-	p0.h = (EVT_EMULATION_ADDR >> 16);
-	p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+	p0.h = (EVT0 >> 16);
+	p0.l = (EVT0 & 0xFFFF);
 	p0 += 8;
 	p1 = 14;
 	r1 = 0;
 	LSETUP(4,4) lc0 = p1;
 	[ p0 ++ ] = r1;
 
-	p0.h = hi(SIC_IWR);
-	p0.l = lo(SIC_IWR);
+	p0.h = hi(SICA_IWR0);
+	p0.l = lo(SICA_IWR0);
 	r0.l = 0x1;
 	w[p0] = r0.l;
 	SSYNC;
@@ -193,8 +197,8 @@ loop1:
 	 */
 
 	/* To keep ourselves in the supervisor mode */
-	p0.l = (EVT_IVG15_ADDR & 0xFFFF);
-	p0.h = (EVT_IVG15_ADDR >> 16);
+	p0.l = (EVT15 & 0xFFFF);
+	p0.h = (EVT15 >> 16);
 
 	p1.l = _real_start;
 	p1.h = _real_start;
@@ -202,8 +206,8 @@ loop1:
 
 	p0.l = (IMASK & 0xFFFF);
 	p0.h = (IMASK >> 16);
-	r0.l = LO(IVG15_POS);
-	r0.h = HI(IVG15_POS);
+	r0.l = LO(EVT_IVG15);
+	r0.h = HI(EVT_IVG15);
 	[p0] = r0;
 	raise 15;
 	p0.l = WAIT_HERE;
@@ -218,13 +222,6 @@ WAIT_HERE:
 _real_start:
 	[ -- sp ] = reti;
 
-#ifdef CONFIG_EZKIT561
-	p0.l = (WDOG_CTL & 0xFFFF);
-	p0.h = (WDOG_CTL >> 16);
-	r0 = WATCHDOG_DISABLE(z);
-	w[p0] = r0;
-#endif
-
 	/* DMA reset code to Hi of L1 SRAM */
 copy:
 	P1.H = hi(SYSMMR_BASE);	/* P1 Points to the beginning of SYSTEM MMR Space */
@@ -235,37 +232,37 @@ copy:
 	R1.H = reset_end;
 	R1.L = reset_end;
 	R2 = R1 - R0;		/* Count */
-	R1.H = hi(L1_ISRAM);	/* Destination Address (high) */
-	R1.L = lo(L1_ISRAM);	/* Destination Address (low) */
+	R1.H = hi(L1_INST_SRAM);	/* Destination Address (high) */
+	R1.L = lo(L1_INST_SRAM);	/* Destination Address (low) */
 	R3.L = DMAEN;		/* Source DMAConfig Value (8-bit words) */
 	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
 
 DMA:
 	R6 = 0x1 (Z);
-	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
-	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
+	W[P1+OFFSET_(IMDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
+	W[P1+OFFSET_(IMDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
 
-	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
-	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
+	[P1+OFFSET_(IMDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
+	W[P1+OFFSET_(IMDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
 	/* Set Source  DMAConfig = DMA Enable,
 	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
-	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+	W[P1+OFFSET_(IMDMA_S0_CONFIG)] = R3;
 
-	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
-	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
+	[P1+OFFSET_(IMDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
+	W[P1+OFFSET_(IMDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
 	/* Set Destination DMAConfig = DMA Enable,
 	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
-	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+	W[P1+OFFSET_(IMDMA_D0_CONFIG)] = R4;
 
 WAIT_DMA_DONE:
-	p0.h = hi(MDMA_D0_IRQ_STATUS);
-	p0.l = lo(MDMA_D0_IRQ_STATUS);
+	p0.h = hi(IMDMA_D0_IRQ_STATUS);
+	p0.l = lo(IMDMA_D0_IRQ_STATUS);
 	R0 = W[P0](Z);
 	CC = BITTST(R0, 0);
 	if ! CC jump WAIT_DMA_DONE
 
 	R0 = 0x1;
-	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
+	W[P1+OFFSET_(IMDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
 
 	/* Initialize BSS Section with 0 s */
 	p1.l = __bss_start;
diff --git a/cpu/bf561/traps.c b/cpu/bf561/traps.c
index 7e2dcd17add..e35620c9aeb 100644
--- a/cpu/bf561/traps.c
+++ b/cpu/bf561/traps.c
@@ -36,14 +36,13 @@
 #include <common.h>
 #include <linux/types.h>
 #include <asm/errno.h>
-#include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/traps.h>
-#include <asm/machdep.h>
 #include "cpu.h"
-#include <asm/arch/anomaly.h>
 #include <asm/cplb.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
 
 void init_IRQ(void)
 {
@@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] =
 void trap_c(struct pt_regs *regs)
 {
 	unsigned int addr;
-	unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
+	unsigned long trapnr = (regs->seqstat) & EXCAUSE;
 	unsigned int i, j, size, *I0, *I1;
 	unsigned short data = 0;
 
@@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs)
 		/* 0x26 - Data CPLB Miss */
 	case VEC_CPLB_M:
 
-#ifdef ANOMALY_05000261
+#if ANOMALY_05000261
 		/*
 		 * Work around an anomaly: if we see a new DCPLB fault, return
 		 * without doing anything.  Then, if we get the same fault again,
@@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs)
 
 		/* Turn the cache off */
 		if (data) {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL &=
 			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-			sync();
+			SSYNC();
 		}
 
 		if (data) {
@@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs)
 		/* Turn the cache back on */
 		if (data) {
 			j = *(unsigned int *)DMEM_CONTROL;
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL =
 			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-			sync();
+			SSYNC();
 		}
 
 		break;