diff options
author | Stefan Roese <sr@denx.de> | 2007-03-21 13:38:59 +0100 |
---|---|---|
committer | Stefan Roese <sr@denx.de> | 2007-03-21 13:38:59 +0100 |
commit | e01bd218b00af73499331a1a701625a852cd286f (patch) | |
tree | efb6d32bfba353b01a07e82f2ef9308b9919e5df /cpu/ppc4xx | |
parent | 87ed3bfb4214c4b39a5a642bcd851f60b3898af2 (diff) |
[PATCH] Add AMCC PPC405EZ support
This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.
Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx')
-rw-r--r-- | cpu/ppc4xx/4xx_enet.c | 3 | ||||
-rw-r--r-- | cpu/ppc4xx/cpu.c | 18 | ||||
-rw-r--r-- | cpu/ppc4xx/cpu_init.c | 3 | ||||
-rw-r--r-- | cpu/ppc4xx/serial.c | 97 | ||||
-rw-r--r-- | cpu/ppc4xx/speed.c | 114 | ||||
-rw-r--r-- | cpu/ppc4xx/start.S | 77 | ||||
-rw-r--r-- | cpu/ppc4xx/usb_ohci.c | 6 | ||||
-rw-r--r-- | cpu/ppc4xx/vecnum.h | 42 |
8 files changed, 323 insertions, 37 deletions
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 4f5558328a2..cf56581d845 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -1333,6 +1333,9 @@ int enetInt (struct eth_device *dev) } } mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ +#if defined(CONFIG_405EZ) + mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); +#endif /* defined(CONFIG_405EZ) */ } while (serviced); diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index b02f6f4eefb..2d8740ccea4 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -47,6 +47,9 @@ void board_reset(void); #if defined(CONFIG_440) #define FREQ_EBC (sys_info.freqEPB) +#elif defined(CONFIG_405EZ) +#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \ + sys_info.pllExtBusDiv) #else #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) #endif @@ -209,7 +212,8 @@ int checkcpu (void) puts("AMCC PowerPC 4"); -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) puts("05"); #endif #if defined(CONFIG_440) @@ -257,6 +261,10 @@ int checkcpu (void) puts("EP Rev. B"); break; + case PVR_405EZ_RA: + puts("EZ Rev. A"); + break; + #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); @@ -386,9 +394,9 @@ int checkcpu (void) } printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), - sys_info.freqPLB / 1000000, - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, - FREQ_EBC / 1000000); + sys_info.freqPLB / 1000000, + get_OPB_freq() / 1000000, + FREQ_EBC / 1000000); if (addstr[0] != 0) printf(" %s\n", addstr); @@ -418,7 +426,7 @@ int checkcpu (void) putc('\n'); #endif -#if defined(CONFIG_405EP) +#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 82ae4434b0b..9d1cd1343d2 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -256,7 +256,8 @@ cpu_init_f (void) */ #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405)) + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405)) /* * Move the next instructions into icache, since these modify the flash * we are running from! diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index fab0d950063..e62dd9dac51 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -264,7 +264,8 @@ int serial_tstc () #endif /* CONFIG_IOP480 */ /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_440) #if defined(CONFIG_440) @@ -309,7 +310,7 @@ int serial_tstc () #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) #endif /* #if defined(CONFIG_440GP) */ -#elif defined(CONFIG_405EP) +#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 #define UCR0_MASK 0x0000007f @@ -392,47 +393,95 @@ volatile static serial_buffer_t buf_info; #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv ) + unsigned short *pbdiv) { - sys_info_t sysinfo; + sys_info_t sysinfo; unsigned long div; /* total divisor udiv * bdiv */ unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ unsigned long i; - unsigned long est; /* current estimate */ + unsigned long est; /* current estimate */ - get_sys_info( &sysinfo ); + get_sys_info(&sysinfo); - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB/(16*baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ + udiv = 32; /* Assume lowest possible serial clk */ + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ + diff = 32; /* highest possible */ /* i is the test udiv value -- start with the largest * possible (32) to minimize serial clock and constrain * search to umin. */ - for( i = 32; i > umin; i-- ){ - ibdiv = div/i; + for (i = 32; i > umin; i--) { + ibdiv = div / i; est = i * ibdiv; idiff = (est > div) ? (est-div) : (div-est); - if( idiff == 0 ){ + if (idiff == 0) { udiv = i; break; /* can't do better */ - } - else if( idiff < diff ){ + } else if (idiff < diff) { udiv = i; /* best so far */ diff = idiff; /* update lowest diff*/ } } *pudiv = udiv; - *pbdiv = div/udiv; + *pbdiv = div / udiv; +} + +#elif defined(CONFIG_405EZ) + +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + unsigned long plloutb; + u32 reg; + + get_sys_info(&sysinfo); + plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv) + / sysinfo.pllFwdDivB); + udiv = 256; /* Assume lowest possible serial clk */ + div = plloutb / (16 * baudrate); /* total divisor */ + umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ + diff = 256; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (256) to minimize serial clock and constrain + * search to umin. + */ + for (i = 256; i > umin; i--) { + ibdiv = div / i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if (idiff == 0) { + udiv = i; + break; /* can't do better */ + } else if (idiff < diff) { + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + mfcpr(cprperd0, reg); + reg &= ~0x0000ffff; + reg |= ((udiv - 0) << 8) | (udiv - 0); + mtcpr(cprperd0, reg); + *pbdiv = div / udiv; } #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */ @@ -518,6 +567,10 @@ int serial_init (void) unsigned short bdiv; volatile char val; +#if defined(CONFIG_405EZ) + serial_divs(gd->baudrate, &udiv, &bdiv); + clk = tmp = reg = 0; +#else #ifdef CONFIG_405EP reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; @@ -548,9 +601,9 @@ int serial_init (void) reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ mtdcr (cntrl0, reg); #endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; +#endif /* CONFIG_405EZ */ out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 06220c34394..028b11af892 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -767,11 +767,119 @@ ulong get_PCI_freq (void) return val; } +#elif defined(CONFIG_405EZ) +void get_sys_info (PPC405_SYS_INFO * sysInfo) +{ + unsigned long cpr_plld; + unsigned long cpr_primad; + unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000); + unsigned long primad_cpudv; + unsigned long m; + + /* + * Read PLL Mode registers + */ + mfcpr(cprplld, cpr_plld); + + /* + * Determine forward divider A + */ + sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16); + + /* + * Determine forward divider B (should be equal to A) + */ + sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8); + if (sysInfo->pllFwdDivB == 0) { + sysInfo->pllFwdDivB = 8; + } + + /* + * Determine FBK_DIV. + */ + sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); + if (sysInfo->pllFbkDiv == 0) { + sysInfo->pllFbkDiv = 256; + } + + /* + * Read CPR_PRIMAD register + */ + mfcpr(cprprimad, cpr_primad); + /* + * Determine PLB_DIV. + */ + sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16); + if (sysInfo->pllPlbDiv == 0) { + sysInfo->pllPlbDiv = 16; + } + + /* + * Determine EXTBUS_DIV. + */ + sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK); + if (sysInfo->pllExtBusDiv == 0) { + sysInfo->pllExtBusDiv = 16; + } + + /* + * Determine OPB_DIV. + */ + sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8); + if (sysInfo->pllOpbDiv == 0) { + sysInfo->pllOpbDiv = 16; + } + + /* + * Determine the M factor + */ + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; + + /* + * Determine VCO clock frequency + */ + sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / + (unsigned long long)sysClkPeriodPs; + + /* + * Determine CPU clock frequency + */ + primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); + if (primad_cpudv == 0) { + primad_cpudv = 16; + } + + sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv; + + /* + * Determine PLB clock frequency + */ + sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv; +} + +/******************************************** + * get_OPB_freq + * return OPB bus freq in Hz + *********************************************/ +ulong get_OPB_freq (void) +{ + ulong val = 0; + + PPC405_SYS_INFO sys_info; + + get_sys_info (&sys_info); + val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv; + + return val; +} + #endif int get_clocks (void) { -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_440) || defined(CONFIG_405) sys_info_t sys_info; get_sys_info (&sys_info); @@ -796,7 +904,9 @@ ulong get_bus_freq (ulong dummy) { ulong val; -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_440) || defined(CONFIG_405) sys_info_t sys_info; get_sys_info (&sys_info); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 24b30dfe716..a50d66e14b6 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -699,7 +699,9 @@ _start: #endif /* CONFIG_IOP480 */ /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405) /*----------------------------------------------------------------------- */ /* Clear and set up some registers. */ /*----------------------------------------------------------------------- */ @@ -727,13 +729,13 @@ _start: /*----------------------------------------------------------------------- */ /* Enable two 128MB cachable regions. */ /*----------------------------------------------------------------------- */ - addis r4,r0,0x8000 - addi r4,r4,0x0001 + lis r4,0x8000 + ori r4,r4,0x0001 mticcr r4 /* instruction cache */ isync - addis r4,r0,0x0000 - addi r4,r4,0x0000 + lis r4,0x0000 + ori r4,r4,0x0000 mtdccr r4 /* data cache */ #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) @@ -755,6 +757,70 @@ _start: #endif /* CONFIG_405EP */ #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) +/* test-only... (clean up later when NAND booting is supported) */ +#if defined(CONFIG_405EZ) + /******************************************************************** + * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 + *******************************************************************/ + /* + * We can map the OCM on the PLB3, so map it at + * CFG_OCM_DATA_ADDR + 0x8000 + */ + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CFG_OCM_DATA_ADDR@l + ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */ + mtdcr ocmplb3cr1,r3 /* Set PLB Access */ + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ + mtdcr ocmplb3cr2,r3 /* Set PLB Access */ + isync + + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CFG_OCM_DATA_ADDR@l + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ + mtdcr ocmdscr1, r3 /* Set Data Side */ + mtdcr ocmiscr1, r3 /* Set Instruction Side */ + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ + mtdcr ocmdscr2, r3 /* Set Data Side */ + mtdcr ocmiscr2, r3 /* Set Instruction Side */ + addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ + mtdcr ocmdsisdpc,r4 + + isync + +#if defined(CONFIG_NAND_SPL) + /* + * 405EZ can boot from NAND Flash. + * If we are booting the SPL (Pre-loader), copy code from + * the mapped 4K NAND Flash to the OCM + */ + li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 + mtctr r4 + lis r2,CFG_NAND_BOOT_SPL_SRC@h + ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l + lis r3,CFG_NAND_BOOT_SPL_DST@h + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l +spl_loop: + lwzu r4,4(r2) + stwu r4,4(r3) + bdnz spl_loop + + /* + * Jump to code in OCM Ram + */ + bl 00f +00: mflr r10 + lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h + ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l + sub r10,r10,r3 + addi r10,r10,28 + mtlr r10 + blr +start_ram: + sync + isync +#endif +#else +/* ...test-only */ /******************************************************************** * Setup OCM - On Chip Memory *******************************************************************/ @@ -774,6 +840,7 @@ _start: addis r4, 0, 0xC000 /* OCM data area enabled */ mtdcr ocmdscntl, r4 isync +#endif /* CONFIG_405EZ */ #endif /*----------------------------------------------------------------------- */ diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c index ab852c525cf..c71a6a9d85a 100644 --- a/cpu/ppc4xx/usb_ohci.c +++ b/cpu/ppc4xx/usb_ohci.c @@ -76,7 +76,7 @@ #define m16_swap(x) swap_16(x) #define m32_swap(x) swap_32(x) -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) +#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX) #define ohci_cpu_to_le16(x) (x) #define ohci_cpu_to_le32(x) (x) #else @@ -1601,7 +1601,7 @@ int usb_lowlevel_init(void) gohci.irq = -1; #if defined(CONFIG_440EP) gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); -#elif defined(CONFIG_440EPX) +#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST) gohci.regs = (struct ohci_regs *)(CFG_USB_HOST); #endif @@ -1625,8 +1625,10 @@ int usb_lowlevel_init(void) ohci_inited = 1; urb_finished = 1; +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) /* init the device driver */ usb_dev_init(); +#endif return 0; } diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index 685d48bcf64..bddf9e5daa9 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -231,6 +231,47 @@ #else /* !defined(CONFIG_440) */ +#if defined(CONFIG_405EZ) +#define VECNUM_D0 0 /* DMA channel 0 */ +#define VECNUM_D1 1 /* DMA channel 1 */ +#define VECNUM_D2 2 /* DMA channel 2 */ +#define VECNUM_D3 3 /* DMA channel 3 */ +#define VECNUM_1588 4 /* IEEE 1588 network synchronization */ +#define VECNUM_U0 5 /* UART0 */ +#define VECNUM_U1 6 /* UART1 */ +#define VECNUM_CAN0 7 /* CAN 0 */ +#define VECNUM_CAN1 8 /* CAN 1 */ +#define VECNUM_SPI 9 /* SPI */ +#define VECNUM_IIC0 10 /* I2C */ +#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */ +#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */ +#define VECNUM_USBH1 13 /* USB Host 1 */ +#define VECNUM_USBH2 14 /* USB Host 2 */ +#define VECNUM_USBDEV 15 /* USB Device */ +#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */ +#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ + +#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ +#define VECNUM_MS 18 /* MAL_SERR_INT */ +#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ +#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ + +#define VECNUM_MTE 19 /* MAL TXEOB */ +#define VECNUM_MTE1 20 /* MAL TXEOB1 */ +#define VECNUM_MRE 21 /* MAL RXEOB */ +#define VECNUM_NAND 22 /* NAND Flash controller */ +#define VECNUM_ADC 23 /* ADC */ +#define VECNUM_DAC 24 /* DAC */ +#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */ +#define VECNUM_RESERVED0 26 /* Reserved */ +#define VECNUM_EIR0 27 /* External interrupt 0 */ +#define VECNUM_EIR1 28 /* External interrupt 1 */ +#define VECNUM_EIR2 29 /* External interrupt 2 */ +#define VECNUM_EIR3 30 /* External interrupt 3 */ +#define VECNUM_EIR4 31 /* External interrupt 4 */ + +#else /* !CONFIG_405EZ */ + #define VECNUM_U0 0 /* UART0 */ #define VECNUM_U1 1 /* UART1 */ #define VECNUM_D0 5 /* DMA channel 0 */ @@ -251,6 +292,7 @@ #define VECNUM_EIR4 29 /* External interrupt 4 */ #define VECNUM_EIR5 30 /* External interrupt 5 */ #define VECNUM_EIR6 31 /* External interrupt 6 */ +#endif /* defined(CONFIG_405EZ) */ #endif /* defined(CONFIG_440) */ |