diff options
| author | Stefan Roese <sr@denx.de> | 2007-08-13 09:05:33 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-13 09:05:33 +0200 |
| commit | 273db7e1bdd1937e32f1d4507321bb721ebd3118 (patch) | |
| tree | 71b1c8710bdfd10dbffca0cf3f0aa0255e064c17 /cpu/ppc4xx/serial.c | |
| parent | 35d22f957a85a22bb3cd1ad084fa5404620d1c42 (diff) | |
ppc4xx: Fix problem in PLL clock calculation
This patch was originall provided by David Mitchell <dmitchell@amcc.com>
and fixes a bug in the PLL clock calculation.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/serial.c')
| -rw-r--r-- | cpu/ppc4xx/serial.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index e62dd9dac5..a75e5eebb3 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -448,12 +448,17 @@ static void serial_divs (int baudrate, unsigned long *pudiv, unsigned long i; unsigned long est; /* current estimate */ unsigned long plloutb; + unsigned long cpr_pllc; u32 reg; + /* check the pll feedback source */ + mfcpr(cprpllc, cpr_pllc); + get_sys_info(&sysinfo); - plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv) - / sysinfo.pllFwdDivB); + plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? + sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / + sysinfo.pllFwdDivB); udiv = 256; /* Assume lowest possible serial clk */ div = plloutb / (16 * baudrate); /* total divisor */ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ |