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authorShinya Kuribayashi <skuribay@ruby.dti.ne.jp>2008-03-25 21:30:07 +0900
committerShinya Kuribayashi <skuribay@ruby.dti.ne.jp>2008-03-25 21:30:07 +0900
commitd43d43ef2845af309c25a64bb9c2c5fb3261bc23 (patch)
tree8110ca5dee67d093aebfee728e838e3fdd89f7d5 /cpu/mpc85xx
parent26138623230ca2bad3c78e05a65527ea70c8b688 (diff)
[MIPS] Initialize CP0 Cause before setting up CP0 Status register
Without this change, we'll be suffering from deffered WATCH exception once Status.EXL is cleared. Make sure Cause.WP is cleared. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'cpu/mpc85xx')
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