diff options
| author | Poonam Aggrwal <poonam.aggrwal@freescale.com> | 2009-10-07 15:47:44 -0400 |
|---|---|---|
| committer | Justin Waters <justin.waters@timesys.com> | 2009-10-07 15:47:44 -0400 |
| commit | 6edfaa93203b8fd6caff435f8ae00080d46fcaea (patch) | |
| tree | 29a08953fe44a88d0adb3dddf953be1312379e4c /cpu/mpc85xx | |
| parent | 7fd9bbc747fdfd038281d9d3d080c8b484b425cd (diff) | |
u-boot-2009.03-p2020rdb-Support-of-P1-P2-processors-v2
Adds support for P20x0 processors of QorIQ series.
The processors are Low end and Ultra Low End products in QorIQ series.
All are e500 based with small variations.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/Makefile | 5 | ||||
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 8 |
2 files changed, 13 insertions, 0 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 99d88a888da..d86fa8f7209 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -1,4 +1,5 @@ # +# Copyright (C) 2009 Freescale Semiconductor, Inc. All Rights Reserved. # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -49,6 +50,10 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_P1020) += ddr-gen3.o +COBJS-$(CONFIG_P1021) += ddr-gen3.o +COBJS-$(CONFIG_P1011) += ddr-gen3.o +COBJS-$(CONFIG_P1012) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 177e35856b9..87d80edf908 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -65,6 +65,14 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(8572, 8572_E, 2, 64), CPU_TYPE_ENTRY(P2020, P2020, 2, 64), CPU_TYPE_ENTRY(P2020, P2020_E, 2, 64), + CPU_TYPE_ENTRY(P1020, P1020, 2, 32), + CPU_TYPE_ENTRY(P1020, P1020_E, 2, 32), + CPU_TYPE_ENTRY(P1021, P1021, 2, 32), + CPU_TYPE_ENTRY(P1021, P1021_E, 2, 32), + CPU_TYPE_ENTRY(P1011, P1011_E, 1, 32), + CPU_TYPE_ENTRY(P1011, P1011_E, 1, 32), + CPU_TYPE_ENTRY(P1012, P1012, 1, 32), + CPU_TYPE_ENTRY(P1012, P1012_E, 1, 32), }; struct cpu_type *identify_cpu(u32 ver) |