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authorAndy Fleming <afleming@freescale.com>2008-02-27 14:29:58 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-02-27 16:28:48 -0600
commit21fae8b2b4e4e6e648796e07e20ab13e9cb18923 (patch)
tree280445d2d3f54d770a75c717247f6d014afb7fd4 /cpu/mpc85xx/start.S
parent347b7938d3e561eb215aa386c37fb5acb5a383c6 (diff)
Invalidate INIT_RAM TLB mappings
Commit 0db37dc... (and some others) changed the INIT_RAM TLB mappings to be unguarded. This collided with an existing "bug" where the mappings for the INIT_RAM were being kept around. This meant that speculative loads to those addresses were succeeding in the TLB, and going out to the bus, where they were causing an exception (there's nothing at that address). The Flash code was coincidentally causing such a speculative load. Rather than go back to mapping the INIT RAM as guarded, we fix it so that the entries for the INIT_RAM are invalidated. Thus the speculative loads will fail in the TLB, and have no effect. Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu/mpc85xx/start.S')
-rw-r--r--cpu/mpc85xx/start.S11
1 files changed, 11 insertions, 0 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index eb24dbc430..636ef5da63 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1007,6 +1007,17 @@ unlock_ram_in_cache:
addi r3,r3,CFG_CACHELINE_SIZE
bdnz 1b
sync /* Wait for all icbi to complete on bus */
+
+ /* Invalidate the TLB entries for the cache */
+ lis r3,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ tlbivax 0,r3
+ addi r3,r3,0x1000
+ tlbivax 0,r3
+ addi r3,r3,0x1000
+ tlbivax 0,r3
+ addi r3,r3,0x1000
+ tlbivax 0,r3
isync
blr
#endif