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authorwdenk <wdenk>2004-02-09 20:51:26 +0000
committerwdenk <wdenk>2004-02-09 20:51:26 +0000
commitb98fff1d6acc57cc54f01740028535ac095237cd (patch)
tree4d9f375a71582a8938e034dcf9082b8f71761b72 /cpu/mpc5xxx
parent5653fc335a450fa46d89989e1afe5e8bb9a0a52e (diff)
* Patch by Rahul Shanbhag, 28 Jan 2004:
Fix flash protection/locking handling for OMAP1610 innovator board. * Patch by Rolf Peukert, 28 Jan 2004: fix flash write problems on CSB226 board (write with 32 bit bus width) * Patches by Mark Jonas, 16 Jan 2004: - fix rounding error when calculating baudrates for MPC5200 PSCs - make sure CFG_RAMBOOT and CFG_LOWBOOT are not enabled at the same time which is not supported
Diffstat (limited to 'cpu/mpc5xxx')
-rw-r--r--cpu/mpc5xxx/serial.c8
-rw-r--r--cpu/mpc5xxx/start.S3
2 files changed, 7 insertions, 4 deletions
diff --git a/cpu/mpc5xxx/serial.c b/cpu/mpc5xxx/serial.c
index 54ecf5be17b..f463d2cf074 100644
--- a/cpu/mpc5xxx/serial.c
+++ b/cpu/mpc5xxx/serial.c
@@ -67,10 +67,10 @@ int serial_init (void)
/* select clock sources */
#if defined(CONFIG_MGT5100)
psc->psc_clock_select = 0xdd00;
- baseclk = CFG_MPC5XXX_CLKIN / 32;
+ baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
#elif defined(CONFIG_MPC5200)
psc->psc_clock_select = 0;
- baseclk = gd->ipb_clk / 32;
+ baseclk = (gd->ipb_clk + 16) / 32;
#endif
/* switch to UART mode */
@@ -85,8 +85,8 @@ int serial_init (void)
psc->mode = PSC_MODE_ONE_STOP;
/* set up UART divisor */
- div = baseclk / gd->baudrate;
- psc->ctur = div >> 8;
+ div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
+ psc->ctur = (div >> 8) & 0xff;
psc->ctlr = div & 0xff;
/* disable all interrupts */
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index a001e1ce404..26811e11ad7 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -104,6 +104,9 @@ boot_warm:
mfmsr r5 /* save msr contents */
#if defined(CFG_LOWBOOT)
+#if defined(CFG_RAMBOOT)
+#error CFG_LOWBOOT is incompatible with CFG_RAMBOOT
+#endif /* CFG_RAMBOOT */
lis r4, CFG_DEFAULT_MBAR@h
lis r3, 0x0000FF00@h
ori r3, r3, 0x0000FF00@l