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authorShinya Kuribayashi <skuribay@ruby.dti.ne.jp>2008-05-30 00:53:38 +0900
committerShinya Kuribayashi <shinya.kuribayashi@necel.com>2008-05-30 00:53:38 +0900
commite2ad8426624bac457acc6925b6ff408e9bf20466 (patch)
treec8659df110945904985611ce85a326ca1e2364cf /cpu/mips
parent1a3adac81c292f2ee76e43cdeb2fbe8f915fe194 (diff)
[MIPS] <asm/mipsregs.h>: Update coprocessor register access macros
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Diffstat (limited to 'cpu/mips')
-rw-r--r--cpu/mips/cpu.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index e267bba4691..0f58d25b892 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -66,10 +66,10 @@ void flush_cache(ulong start_addr, ulong size)
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
{
- write_32bit_cp0_register(CP0_ENTRYLO0, low0);
- write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
- write_32bit_cp0_register(CP0_ENTRYLO1, low1);
- write_32bit_cp0_register(CP0_ENTRYHI, hi);
- write_32bit_cp0_register(CP0_INDEX, index);
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
tlb_write_indexed();
}